Motorola DSP56309 User Manual page 183

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
by the frame sync signal going high). When FSP is set, the frame sync signal polarity is
negative (i.e., the frame start is indicated by the frame sync signal going low).
Either a hardware RESET signal or a software RESET instruction clears FRB.
7.4.2.10 CRB Clock Polarity (CKP) Bit 11
The CKP bit controls on which bit clock edge data and frame sync are clocked out and
latched in. If CKP is cleared, the data and the frame sync are clocked out on the rising
edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If
CKP is set, the data and the frame sync are clocked out on the falling edge of the transmit
bit clock and latched in on the rising edge of the receive bit clock.
Either a hardware RESET signal or a software RESET instruction clears CKP.
7.4.2.11 CRB Synchronous /Asynchronous (SYN) Bit 12
SYN controls whether the receive and transmit functions of the ESSI occur
synchronously or asynchronously with respect to each other; see Figure 7-12
on page 7-20. When SYN is cleared, the ESSI is in asynchronous mode, and separate
clock and frame sync signals are used for the transmit and receive sections. When SYN is
set, the ESSI is in synchronous mode and the transmit and receive sections use common
clock and frame sync signals. Only in synchronous mode can more than one transmitter
be enabled.
Either a hardware RESET signal or a software RESET instruction clears SYN.
7-18 DSP56309UM/D MOTOROLA