Table 10-5 Core Status Bits Description; Once Memory Breakpoint Logic - Motorola DSP56309 User Manual

10.4.3.5 Trace Occurrence (TO) Bit 4
The TO bit is a read-only status bit that is set when debug mode is entered when the
trace counter is zero while trace mode is enabled. This bit is cleared when leaving debug
mode.
10.4.3.6 Reserved OCSR Bit 5
Bit 5 is reserved for future use. It is read as 0 and should be written with 0 for future
compatibility.
10.4.3.7 Core Status (OS0, OS1) Bits 6-7
The OS0, OS1 bits are read-only status bits that provide core status information. By
examining the status bits, the user can determine whether the chip has entered debug
mode. Examining SWO, MBO, and TO identifies the cause of entering debug mode. The
user can also examine these bits and determine the cause why the chip has not entered
debug mode after debug event (DE) assertion or as a result of the execution of the JTAG
debug request instruction (core waiting for the bus, STOP or WAIT instruction, etc.).
These bits are also reflected in the JTAG instruction shift register, which allows the
polling of the core status information at the JTAG level. This is useful when the
DSP56300 core executes the STOP instruction (and therefore there are no clocks) to allow
the reading of OSCR. See Table 10-5 for the definition of the OS0ÐOS1 bits.
OS1
0
0
1
1
10.4.3.8 Reserved Bits 8-23
Bits 8Ð23 are reserved for future use. They are read as 0 and should be written with 0 for
future compatibility.
10.5

OnCE MEMORY BREAKPOINT LOGIC

Memory breakpoints can be set on program memory or data memory locations. In
addition, the breakpoint does not have to be in a specific memory address, but within an
approximate address range where the program may be executing. This significantly
increases the programmerÕs ability to monitor what the program is doing in real time.
MOTOROLA

Table 10-5 Core Status Bits Description

OS0
0 DSP56300 core is executing instructions
1 DSP56300 core is in wait or stop
0 DSP56300 core is waiting for bus
1 DSP56300 core is in debug mode
DSP56309UM/D
On-Chip Emulation Module
OnCE Memory Breakpoint Logic
Description
10-9