Figure 6-15 Interrupt Vector Register (Ivr); Table 6-11 Hreq And Hdrq Settings - Motorola DSP56309 User Manual

Host Interface (HI08)
HI08-External Host ProgrammerÕs Model
HDRQ HREQ
0 0
0 1
1 0
1 1
The HREQ is set from either or both of two conditionsÑeither the receive byte registers
are full or the transmit byte registers are empty. These conditions are indicated by the
ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by
the associated request enable bit in the ICR, HREQ is set if one or more of the two
enabled interrupt sources is set.
6.6.4 Interrupt Vector Register (IVR)
The IVR is an 8-bit, read/write register which typically contains the interrupt vector
number used with MC68000 family processor vectored interrupts. Only the host
processor can read and write this register. The contents of the IVR are placed on the host
data bus, H[7:0], when both the HREQ and HACK signals are asserted. The contents of
this register are initialized to $0F by a hardware RESET signal or software RESET
instruction. This value corresponds to the uninitialized interrupt vector in the MC68000
family. This register is illustrated in Figure 6-15.
6.6.5 Receive Byte Registers (RXH: RXM: RXL)
The receive byte registers are viewed by the host processor as three 8-bit, read-only
registers. These registers are the receive high register (RXH), the receive middle register
(RXM), and the receive low register (RXL). They receive data from the high, middle, and
6-28

Table 6-11 HREQ and HDRQ Settings

HREQ is cleared; no host processor interrupts are requested.
HREQ is set; an interrupt is requested.
HTRQ and HRRQ are cleared, no host processor interrupts are
requested.
HTRQ or HRRQ are set; an interrupt is requested.
7 6 5 4
IV7 IV6 IV5 IV4

Figure 6-15 Interrupt Vector Register (IVR)

DSP56309UM/D
Effect
3 2 1 0
IV3 IV2 IV1 IV0
AA0671
MOTOROLA