Figure 10-5 Once Status And Control Register (Oscr) - Motorola DSP56309 User Manual

On-Chip Emulation Module
OnCE Controller
10.4.2 OnCE Decoder (ODEC)
The ODEC supervises the entire OnCE module activity. It receives as input the 8-bit
command from the OCR, a signal from JTAG Controller (indicating that 8 or 24 bits have
been received and update of the selected data register must be performed), and a signal
indicating that the core was halted. The ODEC generates all the strobes required for
reading and writing the selected OnCE registers.
10.4.3 OnCE Status and Control Register (OSCR)
The OSCR is a 24-bit register used to enable trace mode and to indicate the cause of
entering debug mode. The control bits are read/write while the status bits are read-only.
The OSCR bits are cleared by a hardware RESET signal. The OSCR is shown in
Figure 10-5.
OnCE Status and
Control Register
Read/Write

Figure 10-5 OnCE Status and Control Register (OSCR)

10.4.3.1 Trace Mode Enable (TME) Bit 0
The TME control bit, when set, enables trace mode.
10.4.3.2 Interrupt Mode Enable (IME) Bit 1
The IME control bit, when set, causes the chip to execute a vectored interrupt to the
address VBA:$06 instead of entering debug mode.
10.4.3.3 Software Debug Occurrence (SWO) Bit 2
The SWO bit is a read-only status bit that is set when debug mode is entered because of
the execution of the DEBUG or DEBUGcc instruction with condition true. This bit is
cleared when leaving debug mode.
10.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3
The MBO bit is a read-only status bit that is set when debug mode is entered because a
memory breakpoint has been encountered. This bit is cleared when leaving debug mode.
10-8
23
Indicates reserved bits, written as 0 for future compatibility
DSP56309UM/D
9 8 7 6 5
OS1 OS0
4 3 2 1 0
TO MBO SWO IME TME
AA0705
MOTOROLA