Figure 6-11 Hsr-Hcr Operation; Hi08-External Host Programmerõs Model - Motorola DSP56309 User Manual

Host Interface (HI08)
HI08-External Host ProgrammerÕs Model
routine must read or write the appropriate HI08 register (e.g., clearing HRDF or HTDE)
to clear the interrupt. For host command interrupts, the interrupt acknowledge from the
DSP56309 program controller clears the pending interrupt condition.
15
X:HCR
15
X:HSR
6.6 HI08-EXTERNAL HOST PROGRAMMERÕS MODEL
The HI08 is a simple, high speed interface to a host processor. To the host bus, the HI08
appears to be eight byte-wide registers. Separate transmit and receive data registers are
double-buffered to allow the DSP core and host processor to transfer data efficiently at
high speed. The host can access the HI08 asynchronously by using polling techniques or
interrupt-based techniques.
The HI08 appears to the host processor as a memory-mapped peripheral occupying
eight bytes in the host processor address space, as in Table 6-7 on page 6-22. The eight
HI08 registers include the following:
¥ A control register (ICR)
¥ A status register (ISR)
¥ Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL)
¥ Two vector registers (IVR and CVR)
6-20
Enable
HF3 HF2 HCIE HTIE
HF1 HF0 HCP HTDE HRDF HSR

Figure 6-11 HSR-HCR Operation

DSP56309UM/D
0
HRIE HCR
0
Status
DSP Core Interrupts
Receive Data Full
Transmit Data Empty
Host Command
AA0667
MOTOROLA