Figure 10-7 Once Breakpoint Control Register (Obcr); Table 10-6 Memory Breakpoint 0 And 1 Select Table - Motorola DSP56309 User Manual

On-Chip Emulation Module
OnCE Memory Breakpoint Logic
10.5.6 OnCE Breakpoint Control Register (OBCR)
The OBCR is a 16-bit register used to define the memory breakpoint events. OBCR can
be read or written through the JTAG port. All the bits of the OBCR are cleared by a
hardware RESET signal. The OBCR appears in Figure 10-7.
15
OnCE Breakpoint
Control Register
Reset = $0010
Read/Write
* Indicates reserved bits, written as 0 for future compatibility

Figure 10-7 OnCE Breakpoint Control Register (OBCR)

10.5.6.1 Memory Breakpoint Select (MBS0ÐMBS1)
Bits 0Ð1
The MBS0ÐMBS1 bits enable memory breakpoints 0 and 1, allowing them to occur when
a memory access is performed on P, X, or Y space. See Table 10-6 for the definition of the
MBS0ÐMBS1 bits.

Table 10-6 Memory Breakpoint 0 and 1 Select Table

MBS1 MBS0
0 0
0 1
1 0
1 1
10.5.6.2 Breakpoint 0 Read/Write Select (RW00ÐRW01)
Bits 2Ð3
The RW00ÐRW01 bits define the memory breakpoint 0 to occur when a memory address
access is performed for read, write, or both. See Table 10-7 for the definition of the
RW00ÐRW01 bits.
10-12
14 13 12 11
* * * *
BT1 BT0
Reserved
Breakpoint on P access
Breakpoint on X access
Breakpoint on Y access
DSP56309UM/D
10 9 8 7 6
CC CC RW RW
11 10 11 10
Description
5 4 3 2 1
CC CC RW RW MB
01 00 01 00 S1
MOTOROLA
0
MB
S0
AA0707