Motorola DSP56309 User Manual page 60

Table 2-8 External Bus Control Signals (Continued)
Signal
Type
Name
BB Input/
Output
CAS Output
BCLK Output
BCLK Output
MOTOROLA
State
During
Reset
Input Bus BusyÑBB is a bidirectional active-low
input/output and must be asserted and deasserted
synchronous to CLKOUT. BB indicates that the bus
is active. Only after BB is deasserted can the pending
bus master become the bus master (and then assert
the signal again). The bus master can keep BB
asserted after ceasing bus activity regardless of
whether BR is asserted or deasserted. This is called
Òbus parkingÓ and allows the current bus master to
reuse the bus without rearbitration until another
device requires the bus. The deassertion of BB is
done by an Òactive pull-upÓ method (i.e., BB is
driven high and then released and held high by an
external pull-up resistor).
BB requires an external pull-up resistor.
Tri-stated Column Address StrobeÑWhen the DSP is the bus
master, CAS is an active-low output used by DRAM
to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control
Register is cleared, the signal is tri-stated.
Tri-stated Bus ClockÑWhen the DSP is the bus master, BCLK
is an active-high output. BCLK is active as a
sampling signal when the program address tracing
mode is enabled (by setting the ATE bit in the OMR).
When BCLK is active and synchronized to CLKOUT
by the internal PLL, BCLK precedes CLKOUT by 1/4
of a clock cycle. The BCLK rising edge can be used to
sample the internal program memory access on the
A0ÐA23 address lines.
Tri-stated Bus Clock NotÑWhen the DSP is the bus master,
BCLK is an active-low output and is the inverse of
the BCLK signal. Otherwise, the signal is tri-stated.
DSP56309UM/D
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Signal Description
2-13