Figure 7-10 Essi Frame Sync Generator Functional Block Diagram - Motorola DSP56309 User Manual

RX Word
CRA(DC4:0)
Clock
/1 to /32
0 31
Receive
Control Logic
These signals are
identical in sync mode.
CRB(FSL1:0)
CRB(FSR)
TX Word
Clock CRA(DC4:0)
/1 to /32
0 31
Transmit
Control Logic

Figure 7-10 ESSI Frame Sync Generator Functional Block Diagram

7.4.1.5 CRA Reserved Bit 17
This bit is reserved. It is read as 0 and should be written with 0.
7.4.1.6 CRA Alignment Control (ALC) Bit 18
The ESSI is designed for 24-bit fractional data. Shorter data words are left aligned to the
MSB, Bit 23. For applications that use 16 bit fractional data, shorter data words are left
aligned to bit 15. The ALC bit supports shorter data words. If ALC is set, received words
are left aligned to bit 15 in the receive shift register. Transmitted words must be left
aligned to bit 15 in the transmit shift register. If the ALC bit is cleared, received words
are left aligned to bit 23 in the receive shift register. Transmitted words must be left
aligned to bit 23 in the transmit shift register. The ALC bit is cleared by either a
hardware RESET signal or a software RESET instruction.
Note: If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of
24- or 32-bit words leads to unpredictable results.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
CRB(FSL1)
CRB(FSR)
Internal Rx Frame Sync
Sync
Type
CRB(SCD1) = 1
CRB(SYN) = 0
Receive
Frame Sync
SCD1 = 0
SYN = 1
Internal TX Frame Sync
Sync
Type
Transmit
Frame Sync
DSP56309UM/D
ESSI Programming Model
SYN = 0
SYN = 1
Flag1 In
TX #2, Flag1 Out,
SSISR(IF1)
CRB(TE2) CRB(OF1)
(Sync Mode)
(Sync Mode)
CRB(SCD1)
SCn1
Sync:
TX #2,
Flag1, or
drive enb.
Async:
RX F.S.
or drive enb.
CRA(SSC1)
CRB(SCD2)
SCn2
Sync:
TX/RX F.S.
Async:
TX F.S.
AA0680
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