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9.3.3.1
TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0
These 21 bits contain the current value of the prescaler counter.
9.3.3.2
TPCR Reserved Bits 23-21
These reserved bits are read as 0 and should be written with 0 for future compatibility.
9.3.4
Timer Control/Status Register (TCSR)
The TCSR is a 24-bit, read/write register controlling the timer and reflecting its status.
The register bits are shown in Figure 9-6. The control and status bits are documented in
Table 9-2 on page 9-10.
23
22
21
TCF
11
10
9
DIR
TRM
Ñ reserved, read as 0, should be written with 0 for future compatibility
9.3.4.1
Timer Enable (TE) Bit 0
The TE bit is used to enable or disable the timer. Setting TE enables the timer and clears
the timer counter. The counter starts counting according to the mode selected by the
timer control (TC[3:0]) bit values.
Clearing the TE bit disables the timer. The TE bit is cleared by a hardware RESET signal
or a software RESET instruction.
Note:
When all three timers are disabled and the signals are not in GPIO mode, all
three TIO signals are tri-stated. To prevent undesired spikes on the TIO
signals when switching from tri-state into active state, these signals should be
tied to the high or low signal state by the use of pull-up or pull-down resistors.
9.3.4.2
Timer Overflow Interrupt Enable (TOIE) Bit 1
The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables
overflow interrupt generation. The timer counter can hold a maximum value of
$FFFFFF. When the counter value is at the maximum value and a new event causes the
counter to be incremented to $000000, the timer generates an overflow interrupt.
MOTOROLA
20
19
18
TOF
8
7
6
INV
TC3
TC2
Figure 9-6 Timer Control/Status Register
DSP56309UM/D
Triple Timer Module Programming Model
17
16
15
PCE
5
4
3
TC1
TC0
Triple Timer Module
14
13
12
DO
DI
2
1
0
TCIE
TOIE
TE
9-9
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