11.3.1
Boundary Scan Register (BSR)
The BSR in the DSP56309 JTAG implementation contains bits for all device signal and
clock signals and associated control signals. All DSP56309 bidirectional signals have a
single register bit in the BSR for signal data; each such signal is controlled by an
associated control bit in the BSR. The DSP56309 BSR bit definitions are described in
Table 11-2 on page 11-13.
11.3.2
Instruction Register
The DSP56309 JTAG implementation includes the three mandatory public instructions
(EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional CLAMP
instruction defined by IEEE 1149.1. The HI-Z public instruction provides the capability
for disabling all device output drivers. The ENABLE_ONCE public instruction enables
the JTAG port to communicate with the OnCE circuitry. The DEBUG_REQUEST public
instruction enables the JTAG port to force the DSP56300 core into debug mode. The
DSP56300 core includes a 4-bit instruction register without parity consisting of a shift
register with four parallel outputs. Data is transferred from the shift register to the
parallel outputs during the Update-IR controller state. Figure 11-3 shows the JTAG
instruction register.
The four bits are used to decode the eight unique instructions shown in Table 11-1. All
other encodings are reserved for future enhancements and are decoded as BYPASS.
MOTOROLA
JTAG Instruction
B3
Register (IR)
Figure 11-3 JTAG Instruction Register
DSP56309UM/D
B2
B1
B0
JTAG Port
TAP Controller
AA0746
11-7