On-Chip Program Memory (Program Ram); On-Chip X Data Memory (X Data Ram) - Motorola DSP56309 User Manual

Memory Configuration
RAM Configuration
Memory maps for the different configurations are shown in Figure 3-1 through
Figure 3-8.
Note: The MS bit cannot be changed when CE is set. The instruction cache occupies
the top 1K of what would otherwise be Program RAM; if you switch memory
into or out of Program RAM when the cache is enabled, the switch causes
conflicts. To change the MS bit when CE is set, do the following:
1. Clear CE.
2. Change MS.
3. Set CE.
3.2.1

On-Chip Program Memory (Program RAM)

The on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 20K (default), 23K, 24K, or 19K locations in the program memory
space (depending on the settings of the MS and CE bits). The Program RAM default
organization is 80 banks of 256 24-bit words (20K). The upper eight banks of both X data
RAM and Y data RAM can be configured as Program RAM by setting the MS bit. When
the CE is set, the upper 1K of Program RAM is used as an internal Instruction Cache.
While the contents of Program RAM are unaffected by toggling the
MS bit, the location of program data placed in the Program
RAM/Instruction Cache area changes after the MS bit is toggled, since
the cache always occupies the top-most 1K Program RAM addresses.
To preserve program data integrity, do not set or clear the MS bit
when the CE bit is set. See Section 3.2 on page 3-5 for the correct
procedure.
3.2.2

On-Chip X Data Memory (X Data RAM)

The on-chip X data RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 7K (default) or 5K locations in the X memory space. The size of the
X data RAM depends on the setting of the MS bit (default: MS is cleared). The X data
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can
be switched from the X data RAM to the Program RAM by setting the MS bit (leaving 5K
of X data RAM).
3-6
CAUTION
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