Motorola DSP56309 User Manual page 206

Transmitter 1 and transmitter 2 operate only in synchronous mode. Data clock and
frame sync signals can be generated internally by the DSP or can be obtained from
external sources. If clocks are internally generated, the ESSI clock generator derives bit
clock and frame sync signals from the DSP internal system clock. The ESSI clock
generator consists of a selectable fixed prescaler with a programmable prescaler for bit
rate clock generation and a programmable frame-rate divider with a word-length
divider for frame-rate sync-signal generation.
7.5.4.3 Frame Sync Selection
The transmitter and receiver can operate independently. The transmitter can have either
a bit-long or word-long frame-sync signal format, and the receiver can have the same or
another format. The selection is made by programming FSL[1:0], FSR, and FSP bits in the
CRB.
7.5.4.3.1 Frame Sync Signal Format
FSL1 controls the frame-sync signal format.
¥ If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data
transfer period. This frame sync length is compatible with Motorola codecs, serial
peripherals that conform to the Motorola SPI, serial A/D and D/A converters,
shift registers, and telecommunication pulse code modulation (PCM) serial I/O.
¥ If the FSL1 bit is set, the RX frame sync pulses active for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel
and National components, codecs, and telecommunication PCM serial I/O.
7.5.4.3.2 Frame Sync Length for Multiple Devices
The ability to mix frame sync lengths is useful in configuring systems in which data is
received from one type of device (e.g., codec) and transmitted to a different type of
device. FSL0 controls whether RX and TX have the same frame sync length.
¥ If the FSL0 bit is cleared, both RX and TX have the same frame sync length.
¥ If the FSL0 bit is set, RX and TX have different frame sync lengths.
FSL0 is ignored when the SYN bit is set.
7.5.4.3.3 Word-Length Frame Sync and Data-Word Timing
The FSR bit controls the relative timing of the word-length frame sync relative to the
data word timing.
¥ When the FSR bit is cleared, the word length frame sync is generated (or
expected) with the first bit of the data word.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
DSP56309UM/D
Operating Modes
7-41