Motorola DSP56309 User Manual page 342

M_DSR4 EQU $FFFFDF
M_DDR4 EQU $FFFFDE
M_DCO4 EQU $FFFFDD
M_DCR4 EQU $FFFFDC
; Register Addresses Of DMA5
M_DSR5 EQU $FFFFDB
M_DDR5 EQU $FFFFDA
M_DCO5 EQU $FFFFD9
M_DCR5 EQU $FFFFD8
; DMA Control Register
M_DSS EQU $3
;(DSS0-Dss1)
M_DSS0 EQU 0
M_DSS1 EQU 1
M_DDS EQU $C
;(DDS-DDS1)
M_DDS0 EQU 2
M_DDS1 EQU 3
M_DAM EQU $3f0
;(DAM5-DAM0)
M_DAM0 EQU 4
M_DAM1 EQU 5
M_DAM2 EQU 6
M_DAM3 EQU 7
M_DAM4 EQU 8
M_DAM5 EQU 9
M_D3D EQU 10
M_DRS EQU $F800
M_DCON EQU 16
M_DPR EQU $60000
M_DPR0 EQU 17
M_DPR1 EQU 18
M_DTM EQU $380000
;(DTM2-DTM0)
M_DTM0 EQU 19
M_DTM1 EQU 20
M_DTM2 EQU 21
M_DIE EQU 22
M_DE EQU 23
MOTOROLA
; DMA4 Source Address Register
; DMA4 Destination Address Register
; DMA4 Counter
; DMA4 Control Register
; DMA5 Source Address Register
; DMA5 Destination Address Register
; DMA5 Counter
; DMA5 Control Register
; DMA Source Space Mask
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode Mask
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
; DMA Address Mode 5
; DMA Three Dimensional Mode
; DMA Request Source Mask (DRS0-DRS4)
; DMA Continuous Mode
; DMA Channel Priority
; DMA Channel Priority Level (low)
; DMA Channel Priority Level (high)
; DMA Transfer Mode Mask
; DMA Transfer Mode 0
; DMA Transfer Mode 1
; DMA Transfer Mode 2
; DMA Interrupt Enable bit
; DMA Channel Enable bit
DSP56309UM/D
Equates
B-11