Figure 9-5 Timer Prescaler Count Register (Tpcr); Table 9-1 Prescaler Source Selection - Motorola DSP56309 User Manual

Triple Timer Module
Triple Timer Module Programming Model
If the prescaler source clock is external, the prescaler counter is incremented by signal
transitions on the TIO signal. The external clock is internally synchronized to the internal
clock. The external clock frequency must be lower than the DSP56309 internal operating
frequency divided by 4 (CLK/4).
The PS[1:0] bits are cleared by a hardware RESET signal or a software RESET instruction.
Note: To insure proper operation, change the PS[1:0] bits only when the prescaler
counter is disabled. Disable the prescaler counter by clearing the TE bit in the
TCSR of each of three timers.
PS1
9.3.2.3 TPLR Reserved Bit 23
This reserved bit is read as 0 and should be written with 0 for future compatibility.
9.3.3 Timer Prescaler Count Register (TPCR)
The TPCR is a 24-bit, read-only register that reflects the current value in the prescaler
counter. The register bits are shown in Figure 9-5.
23 22 21
11 10 9
PC11 PC10 PC9
Ñ reserved, read as 0, should be written with 0 for future compatibility

Figure 9-5 Timer Prescaler Count Register (TPCR)

9-8

Table 9-1 Prescaler Source Selection

PS0
0 0
0 1
1 0
1 1
20 19 18
PC20 PC19 PC18
8 7 6
PC8 PC7 PC6
DSP56309UM/D
Prescaler Clock Source
Internal CLK/2
TIO0
TIO1
TIO2
17 16 15
PC17 PC16 PC15
5 4 3
PC5 PC4 PC3
14 13 12
PC14 PC13 PC12
2 1 0
PC2 PC1 PC0
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