Figure 9-4 Timer Prescaler Load Register (Tplr) - Motorola DSP56309 User Manual

9.3.1 Prescaler Counter
The prescaler counter is a 21-bit counter that is decremented on the rising edge of the
prescaler input clock. The counter is enabled when at least one of the three timers is
enabled (i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler
output as its source (i.e., one or more of the PCE bits are set).
9.3.2 Timer Prescaler Load Register (TPLR)
The TPLR is a 24-bit, read/write register that controls the prescaler divide factor (i. e.,
the number that the prescaler counter loads and begins counting from) and the source
for the prescaler input clock. The control bits are shown below in Figure 9-4.
23 22 21
PS1 PS0
11 10 9
PL11 PL10 PL9
Ñ reserved, read as 0, should be written with 0 for future compatibility

Figure 9-4 Timer Prescaler Load Register (TPLR)

9.3.2.1 TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0
These 21 bits contain the prescaler preload value. This value is loaded into the prescaler
counter when the counter value reaches 0, or the counter switches state from disabled to
enabled.
If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a
prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1.
The PL[20:0] bits are cleared by a hardware RESET signal or a software RESET
instruction.
9.3.2.2 TPLR Prescaler Source (PS[1:0]) Bits 22-21
The two PS bits control the source of the prescaler clock. Table 9-1 summarizes PS bit
functionality. The prescalerÕs use of a TIO signal is not affected by the TCSR settings of
the timer corresponding to the TIO signal being used.
MOTOROLA
20 19 18
PL20 PL19 PL18
8 7 6
PL8 PL7 PL6
DSP56309UM/D
Triple Timer Module Programming Model
17 16 15
PL17 PL16 PL15
5 4 3
PL5 PL4 PL3
Triple Timer Module
14 13 12
PL14 PL13 PL12
2 1 0
PL2 PL1 PL0
9-7