Host Interrupts Using Host Request (Horeq); Polling - Motorola DSP56012 User Manual

Parallel Host Interface
Host Interface (HI)
3. strobes the data transfer using HEN.
When data is being written to the HI by the host processor, the positive-going edge of
HEN latches the data in the selected HI register. When data is being read by the host
processor, the negative-going edge of HEN strobes the data onto the data bus
H0–H7. This process is illustrated in Figure 4-16 on page 4-40. The timing
relationships are specified in the DSP56012 Technical Data sheet .
4.4.7.2

Host Interrupts using Host Request (HOREQ)

The host processor interrupts are external and use the HOREQ pin. HOREQ is
normally connected to the host processor maskable interrupt input (IPL0, IPL1, or
IPL2 in Figure 4-17 on page 4-41). The host processor acknowledges host interrupts
by executing an interrupt service routine. The Most Significant Bit (HOREQ) of the
ISR can be tested by the host processor to determine if the DSP is the interrupting
device and the two Least Significant Bits (RXDF and TXDE) can be tested to
determine the interrupt source (see Figure 4-21 on page 4-45). The host processor
interrupt service routine must read or write the appropriate HI register to clear the
interrupt. HOREQ is deasserted when one of the following occurs:
• the enabled request is cleared or masked,
• DMA HACK is asserted, or
• the DSP is reset.
4.4.7.3

Polling

In the Polling mode of operation, the HOREQ pin is not connected to the host
processor and HACK must be deasserted to insure DMA data or IVR data is not
being output on H0–H7 when other registers are being polled.
The host processor first performs a data read transfer to read the ISR (see Figure 4-16
on page 4-40) to determine, whether:
1. RXDF = 1, signifying the receive data register is full and, therefore, a data read
should be performed.
2. TXDE = 1, signifying the transmit data register is empty so that a data write
can be performed.
3. TRDY = 1, signifying the transmit data register is empty and that the receive
data register on the DSP CPU side is also empty so that the data written by the
host processor will be transferred directly to the DSP side.
4. HF2 HF3
CPU has been reached, and requires action on the part of the host processor.
4-38
0, signifying that an application-specific state within the DSP
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