Operation On Hardware Reset; Figure 3-7 Pll Configuration - Motorola DSP56012 User Manual

Memory, Operating Modes, and Interrupts

Operation on Hardware Reset

EXTAL
Phase
Detector
(PD)
3.8

OPERATION ON HARDWARE RESET

The processor enters the Reset processing state when the external RESET pin is
asserted (hardware reset occurs). The Reset state:
• resets internal peripheral devices and initializes their control registers as
described in the peripheral sections,
• sets the modifier registers to $FFFF,
• clears the Interrupt Priority Register,
• clears the Stack Pointer,
• clears the Scaling mode, Trace mode, Loop Flag, Double Precision Multiply
mode and condition code bits, and sets the interrupt mask bits of the Status
Register (SR), and
• clears the Stop Delay (SD) bit and the Program RAM Enable (PEA and PEB)
bits in the OMR.
The DSP remains in the Reset state until the RESET pin is deasserted. When the
processor leaves the Reset state it:
• loads the chip operating mode bits of the OMR from the external mode select
pins (MODC, MODB, MODA), and
• begins program execution of the bootstrap ROM starting at address $0000.
3-20
Charge Voltage
Pump Controlled
Loop Oscillator
Filter (VCO)
Frequency
Multiplier
Multiplication
Factor
1 to 4096
MF[11:0]

Figure 3-7 PLL Configuration

DSP56012 User's Manual
Low
Power
Divider Out
Divider
0 15
2 to 2
DF[3:0]
VCO Out
AA0293k
MOTOROLA