Motorola DSP56012 User Manual page 71

Table 3-2 Internal I/O Memory Map (Continued)
Location
X: $FFF5
X: $FFF4
X: $FFF3
X: $FFF2
X: $FFF1
X: $FFF0
X: $FFEF
X: $FFEE
X: $FFED
X: $FFEC
X: $FFEB
X: $FFEA
X: $FFE9
X: $FFE8
X: $FFE7
X: $FFE6
X: $FFE5
X: $FFE4
X: $FFE3
X: $FFE2
X: $FFE1
X: $FFE0
X: $FFDF
X: $FFDE
X: $FFDD
X:$FFDC
X:$FFDB–FFC0
MOTOROLA
Reserved
Reserved
SHI Receive FIFO/Transmit Register (HRX/HTX)
2
SHI I C Slave Address Register (HSAR)
SHI Host Control/Status Register (HCSR)
SHI Host Clock Control Register (HCKR)
Reserved
Port B Data Register (PBD)
Port B Data Direction Register (PBDDR)
Port B Control Register (PBC)
Host Receive/Transmit Register (HORX/HOTX)
Reserved
Host Status Register (HSR)
Host Control Register (HCR)
SAI TX2 Data Register (TX2)
SAI TX1 Data Register (TX1)
SAI TX0 Data Register (TX0)
SAI TX Control/Status Register (TCS)
SAI RX1 Data Register (RX1)
SAI RX0 Data Register (RX0)
SAI RX Control/Status Register (RCS)
SAI Baud Rate Control Register (BRC)
DAX Status Register (XSTR)
DAX Control Register (XCTR)
Reserved
DAX Transmit Data Registers (XADRA and XADRB)
Reserved
DSP56012 User's Manual
Memory, Operating Modes, and Interrupts
DSP56012 Data and Program Memory Maps
Register
3-11