Host Interface (Hi); Figure 4-6 I/O Port B Configuration - Motorola DSP56012 User Manual

Step 1. Activate Port B For General Purpose I/O:
Write 0s to Bits 0 And 1
15
X:$FFEC
Step 2. Set Individual Pins To Input Or Output:
BDxx = 0
or
BDxx = 1
15
X:$FFED
Step 3. Write Or Read Data:
PDxx Input if BDxx = 0
or
PDxx Output if BDxx = 1
15
X:$FFEE
Reserved; write as 0
Note: The Port B GPIO timing differs from the timing of the GPIO peripheral. Please
refer to the DSP56012 Technical Data sheets for the timing specifications.
4.4

HOST INTERFACE (HI)

The Host Interface (HI) is a byte-wide, full-duplex, double-buffered, parallel port
that can be connected directly to the data bus of a host processor to be used primarily
as a parallel data transfer port. The host processor can be any of a number of
industry-standard microcomputers or microprocessors, another DSP, or Direct
Memory Address (DMA) devices because this interface looks like static memory to
those devices. The HI is asynchronous and consists of two banks of registers—one
bank accessible to the host processor and a second bank accessible to the DSP Central
Processing Unit (CPU) (see Figure 4-7 on page 4-12).
Note: Unlike other DSPs in this Motorola family, this device uses the SHI for a host
control interface, and the HI as a high-speed parallel data transfer interface.
MOTOROLA
Input
Output
BD BD BD BD BD BD BD
14 13 12 11 10 9 8
PB PB PB PB PB PB PB
14 13 12 11 10 9 8

Figure 4-6 I/O Port B Configuration

DSP56012 User's Manual
BC
1
BD BD BD BD BD BD BD
7 6 5 4 3 2 1
PB PB PB PB PB PB PB
7 6 5 4 3 2 1
Parallel Host Interface
Host Interface (HI)
0
Port B
BC
Control Register (PBC)
0
0
Port B Data Direction
BD
Register (PBDDR)
0
0
Port B Data
PB
register (PBD)
0
AA0312.11
4-9