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5. Assert HEN to enable the HI.
6. When HEN is deasserted, the data can be latched or read as appropriate if the
timing requirements have been observed.
7. HOREQ will be deasserted if the operation is complete.
This transfer description is an overview. Specific and exact information for HI data
transfers and their timing can be found in 4.4.8.3 DMA Data Transfer and in the
D SP56012 Technical Data sheet (DSP56012/D) .
Step 2 Of Host Port configuration
2. Option 5: Select DMA mode for
Initialize DSP
Initialize HI *
Bit 7 = 1
24-bit DMA
Bit 5 = 1
Bit 6 = 0
OR
16-bit DMA
Bit 5 = 0
Bit 6 = 1
OR
DMA off
Bit 5 = 1
Bit 6 = 1
7
6
$0
INIT
HM1
*See Figure 4-26.
Reserved; write as 0
Figure 4-24 HI Initialization–Host Side, DMA Mode
MOTOROLA
DSP TO HOST
OR
HOST TO DSP
Optional
5
4
3
2
HM0
HF1
HF0
DSP56012 User's Manual
Parallel Host Interface
enable
Receive Data Full interrupt
Bit 0 = 1
Bit 1 = 0
enable
Transmit Data Empty interrupt
Bit 0 = 0
Bit 1 = 1
1
0
INTERRUPT CONTROL REGISTER (ICR)
TREQ
RREQ
(read/write)
Host Interface (HI)
AA0332k
4-47
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