Motorola DSP56012 User Manual page 62

Memory, Operating Modes, and Interrupts
SECTION 3
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 DSP56012 DATA AND PROGRAM MEMORY . . . . . . . . . . . 3-3
3.2.1 X and Y Data ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3 DSP56012 DATA AND PROGRAM MEMORY MAPS . . . . . 3-4
3.3.1 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.2 Dynamic Switch of Memory Configurations . . . . . . . . . . . 3-7
3.3.3 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . 3-11
3.4.1 DSP Operating Mode (MC, MB, MA)-Bits 4, 1, and 0. . 3-11
3.4.2 Program RAM Enable A (PEA)-Bit 2 . . . . . . . . . . . . . . 3-11
3.4.3 Program RAM Enable B (PEB)-Bit 3 . . . . . . . . . . . . . . 3-11
3.4.4 Stop Delay (SD)-Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.6 INTERRUPT PRIORITY REGISTER. . . . . . . . . . . . . . . . . . 3-14
3.7 PHASE LOCK LOOP (PLL) CONFIGURATION . . . . . . . . . 3-18
3.8 OPERATION ON HARDWARE RESET . . . . . . . . . . . . . . . 3-19
3-2
MEMORY, OPERATING MODES,
AND INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DSP56012 User's Manual MOTOROLA