Motorola DSP56012 User Manual page 34

24-bit digital signal processor
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Overview
DSP56012 Architectural Overview
Table 1-3 Interrupt Starting Addresses and Sources (Continued)
Interrupt
Starting Address
P:$000E
P:$0010
P:$0012
P:$0014
P:$0016
P:$0018
P:$001A
P:$001C
P:$001E
P:$0020
P:$0022
P:$0024
P:$0026
P:$0028
P:$002A
P:$002C
P:$002E
P:$0030
P:$0032
P:$0034
P:$0036
:
P:$003C
P:$003E
P: $0040
P: $0042
P: $0044
P: $0046
P: $0048
P: $004A
P: $004C
P: $004E
1-14
IPL
Reserved
0–2
SAI Left Channel Transmitter if TXIL = 0
0–2
SAI Right Channel Transmitter if TXIL = 0
0–2
SAI Transmitter Exception if TXIL = 0
0–2
SAI Left Channel Receiver if RXIL = 0
0–2
SAI Right Channel Receiver if RXIL = 0
0–2
SAI Receiver Exception if RXIL = 0
Reserved
3
NMI
0–2
SHI Transmit Data
0–2
SHI Transmit Underrun Error
0–2
SHI Receive FIFO Not Empty
Reserved
0–2
SHI Receive FIFO Full
0–2
SHI Receive Overrun Error
0–2
SHI Bus Error
Reserved
0–2
Host Receive Data
0–2
Host Transmit Data
0–2
Host Command (default)
Reserved; available for Host Command, see p. B-5–B-6.
:
Reserved; available for Host Command, see p. B-5–B-6.
3
Illegal Instruction
0–2
SAI Left Channel Transmitter if TXIL = 1
0–2
SAI Right Channel Transmitter if TXIL = 1
0–2
SAI Transmitter Exception if TXIL = 1
0–2
SAI Left Channel Receiver if RXIL = 1
0–2
SAI Right Channel Receiver if RXIL = 1
0–2
SAI Receiver Exception if RXIL = 1
Reserved; available for Host Command, see p. B-5–B-6.
Reserved; available for Host Command, see p. B-5–B-6.
DSP56012 User's Manual
Interrupt Source
MOTOROLA

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