Hi-Dsp Viewpoint; Figure 4-7 Hi Block Diagram - Motorola DSP56012 User Manual

Parallel Host Interface
Host Interface (HI)
•
Host MPU
8
Data Bus
H[7:0]
4.4.3 HI—DSP Viewpoint
The DSP views the HI as a memory-mapped peripheral occupying three 24-bit words
in data memory space. The DSP accesses the HI using either standard polled or
interrupt programming techniques. Separate transmit and receive data registers are
double-buffered to allow the DSP and host processor to transfer data efficiently at
high speed. Memory mapping allows communication with the HI registers to use
4-12
Interrupt Control
Register
$0
(Read/Write)
ICR
Command Vector
$1
Register
CVR
(Read/Write)
Interrupt Status
$2
Register
ISR
(Read Only)
Interrupt Vector
$3
Register
IVR
(Read/write)
Receive Byte
Registers
$5
RXH
(Read Only)
24
$6
RXM
$7
RXL
Transmit Byte
Registers
$5
(Write Only)
TXH
24
$6
TXM
$7
TXL

Figure 4-7 HI Block Diagram

DSP56012 User's Manual
DSP CPU Global
Data Bus
X:$FFE8
Host Control Register
HCR
(Read/Write)
X:$FFE9
Host Status Register
HSR
(Read Only)
Control
Logic
X:$FFEB
Host Transmit
HOTX
Data Register
(Write Only)
24
X:$FFEB
Host Recieve
HORX
Data Register
(Read Only)
AA0313k
MOTOROLA