Table 4-16 Word-To-Physical-Address Mapping For Dram Absolute; Dram Refresh - Motorola DSP56009 User Manual

Addressing modes are not acceptable. Table 4-16 summarizes the address generation
for DRAM absolute addressing.
Table 4-16 Word-to-Physical-Address Mapping for DRAM Absolute Addressing
DRAM
EAM[3:0]
size
1100 64 K
1101 256 K
1110 1 M
1111 4 M
4.4

DRAM REFRESH

DRAM devices require periodic refresh of the data stored in their memory cells
(typically every few milliseconds). The EMI can carry out DRAM refresh either by
accessing the memory cells frequently enough, or by using dedicated DRAM refresh
accesses. The EMI is capable of generating CAS before RAS refresh cycles
automatically or under software control. The refresh cycle insertion rate is controlled
by a programmable refresh timer. Refer to Section 4.4.5 DRAM Refresh Timing for
more details on DRAM refresh requirements.
There are four ways to refresh a DRAM memory connected to the EMI. The way in
which the refresh is achieved has a major influence on the EMI real-time performance
and on the EMI channel bandwidth.
4.4.1 DRAM Refresh Without Using The Internal Refresh Timer
It is possible to refresh the DRAM by data access itself if a sufficient number of
accesses are performed in the required refresh time, and all rows are accessed. This,
however, must be assured. The EMI address translation is performed in such a way
that it is possible to satisfy these requirements by carefully choosing the base
addresses of the different data-delay buffers.
MOTOROLA
ROW/ EWL
EBW MA10 MA9 MA8 MA7 MA[6:3] MA2 MA1 MA0
COL [2:0]
R — —
C XXX X
R — —
C XXX X
R — —
C XXX X
R — — A10
C XXX X A21 A20 A19 A18 A[17:14] A13 A12 A11
DSP56009 User's Manual
External Memory Interface
0 0 0 A7
0 0 0 A15 A[14:11] A10 A9
0 0 A8 A7
0 0 A17 A16 A[15:12] A11 A10 A9
0 A9 A8 A7
0 A19 A18 A17 A[16:13] A12 A11 A10
A9 A8 A7
DRAM Refresh
A[6:3] A2 A1 A0
A8
A[6:3] A2 A1 A0
A[6:3] A2 A1 A0
A[6:3] A2 A1 A0
4-31