Motorola DSP56009 User Manual page 13

Figure 1-1 DSP56009 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Figure 2-1 DSP56009 SIgnals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 3-1 Memory Maps for PEA = 0, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-2 Memory Maps for PEA = 1, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-3 Memory Maps for PEA = 0, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-4 Memory Maps for PEA = 1, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-5 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-6 Interrupt Priority Register (Address X:$FFFF). . . . . . . . . . . . . . 3-14
Figure 3-7 PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Figure 4-1 EMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-2 EMI Control/Status Register (ECSR). . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-3 EMI Refresh Control Register (ERCR) . . . . . . . . . . . . . . . . . . . 4-21
Figure 4-4 EMI Address Generation Block Diagram. . . . . . . . . . . . . . . . . . 4-23
Figure 4-5 Refresh Timer Functional Diagram.. . . . . . . . . . . . . . . . . . . . . . 4-33
Figure 4-6 Timing Diagram of a DRAM Refresh Cycle (Fast). . . . . . . . . . . 4-37
Figure 4-7 Timing Diagram Of a DRAM Refresh Cycle (Slow). . . . . . . . . . 4-37
Figure 4-8 EMI Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Figure 4-9 Illustration of the Data-Delay Structure . . . . . . . . . . . . . . . . . . . 4-46
Figure 4-10 DRAM for Data Delay Buffers and for SRAM for Bootstrap . . . 4-48
Figure 4-11 SRAM for Data Delay Buffers and for Bootstrap. . . . . . . . . . . . 4-49
MOTOROLA
LIST OF FIGURES
DSP56009 User's Manual xi