Motorola DSP56600 Manual page 69

Instruction Cache and Memory Features
The Instruction Cache
5-8 Optimizing DSP56300/DSP56600 Applications
Table 5-2 Cycle Count Example With and Without Burst Mode
No Instruction
i11 mac x0,y0,a x:(r0)+,x0
i12 macr x0,y0,a
i13 nop
i14 move
i15 nop
i16 nop
i17 nop
i0 nop
During non-burst pipeline operation, while an instruction is
executing (i.e., in the instruction latch), the external memory port
may be busy with the following accesses:
1. Fetching an external program word of the next instruction (1
access at most)
2. Data reads/writes for the instruction 3 words back (2
accesses at most)
For example, during the execution of instruction i4, the memory
port is busy with the data transfers of i1, and fetching of i5. In order
to calculate the cycle count of an instruction in the example, we
should add the cycle count of the accesses that are performed
during its execution. An access cycle count is the number of wait
states + 1. The instruction's execution time is in parallel to the access
cycles.
Example 5-1 Example for i5
1 out-of-page data access
1 in-page data access
1 out-of-page program access
This information is specific for this example (in 2-word or
Note:
multi-cycle instructions the behavior may change), and
brought only to explain the cycle count in the table.
Burst Mode
Disabled
External
Accesses
y:(r4)+,y0 1do,1di,1po
1do,1di,1po
1do,1po
a,y:(r1)+ 1do,1di,1po
1pi
1pi
1do
TOTAL:
1po
total:
Burst Mode
Enabled
External
Cyc Cyc
Accesses
21 2di 6
21 2di,1po,3pi 24
18 1do 9
21 2di 6
3 —
3 1po,3pi 18
9 1do 9
257 — 186
9 1po,3pi 15
9 cycles
3 cycles
9 cycles
21 cycles
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