Back End Module; System On Module(Som); Master Control Board(Mst) - GE LOGIQ A3 Basic Service Manual

GE H
EALTHCARE
D 5213326-100, R
IRECTION
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Back End Module

The Back End Module consists following two PCB's:
1.) System On Module
2.) Master Control Board
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System On Module(SOM)

This module consists of a System On Module (SOM), which is mainly responsible for backend
processing and storing of patient data.
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Master Control Board(MST)

MST board is the central processing unit of the Logiq-Uno system. It includes a TMS320C6415T digital
signal processor for front-end data processing (mainly scan conversion) of receive signals and scan
setup and control.
The OQX2 beam former output of TxRx board is connected to Chafcom ip. CHACOM- CHAF + COMSO
CHAF is Coded decoder and filter for Tissue Harmonics. The COMSO includes filters, demodulator,
detector, rate conversion, edge enhance and its controls. Data FPGA controls the chafcom interface
and initializes all the chafcom registers with default data on poweron. DSP based on command from
SOM updates the DPRAM region in data fpga whenever user changes DRC, Edge enhancement, Gain,
Frequency and TGC. DataFpga based on command updates these data to chafcom during Trig high
period.
The output of Chafcom scan line wise is stored in DPRAM implemented in Data Fpga. DSP reads this
image data in polar coordinates from Data Fpga Dpram and stores in internal memory. DSP performs
scan conversion, bilinear interpolation on the data in polar format to XY format. The final data is
transferred to SOM SDRAM using PCI bus DMA protocol.
DSP6415 firmware controls the scan setup and sequence. DSP sets up the scan based on Trig interrupt
from FPGA. The trig low time depends on the ultrasound depth set by the user. Scan setup happens
during trig high time. DSP writes the TPG2, Oqx2 register values required for the current scan line to
Control FPGA DPRAM. Control FPGA reads the DPRAM values and updates the ASIC with the new
set of data. Control FPGA generates the necessary signals required to meet the timing specs for the
Asic. MST Control FPGA interfaces with Connector Board FPGA with predefined protocol. DSP updates
on probe change request, and HV mux start element values are written from control fpga to connector
board fpga every trig. Connector board FPGA in turn returns the probe code value and other status to
MST FPGA.
DSP code resides in the flash memory. DSP copies the data from flash memory to internal memory and
executes the code. CPLD controls the DSP flash interface. DSP SDRAM stores probe related IQ
resource data.
MST has DC-DC regulators, which generate the voltages required by on board devices. MST has
voltage monitoring circuit which monitors all the voltages in the system and the information is passed
on to control FPGA. DSP reads this information and sends these data to system software for user alerts.
MST has clock generation circuitry which generates all the clock signals these signals are used to
generate all the clocks used by DSP, Fpgas, chafom, oqx2,tpg2 and connector board.
VCA_control signal is generated by DAC circuit based data from control fpga.
MST also has an interface to the SOMA255F, which is mainly responsible for backend processing, user
interface and storing of patient data. SOMA255F has PCI 2.2 support and supports 2 USB ports of
USB1.1. These 2 ports are connected to rear panel of the system. MST has a USB 2.0 controller device
connected on PCI bus. This controller provides 4 more USB downstream ports which are connected to
front panel and top panel and for CD drive. System has a video play back device connected on pci bus.
MST also has VGA, Digital RGB to composite video, S video output conversion circuit which is
connected to rear panel.
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Approv e d Docu m ent - 5213326-100TPH_r3.pdf Page 109 of 252
3
EVISION
Section 5-2 - Block Diagrams and Theory
LOGIQ™ A3 S M
ERVICE ANUAL