Cyclic Transmission; 32-Bit Data Assurance - Mitsubishi Electric Melsec QJ71LP21 Reference Manual

6 PROGRAMMING

6.2 Cyclic Transmission

6.2.1 32-bit data assurance

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The link scan of MELSECNET/H and the sequence scan of the programmable
controller operate asynchronously.
Thus, the link refresh executed per sequence scan is asynchronous with the link scan.
Depending on the timing of the link refresh, link data with data types of more than 32
bits (two words), such as the ones below, may be broken up into new and old data,
which may coexist in 16-bit (one word) units.
• Floating point data
• Current values of positioning module, command speed.
The MELSECNET/H provides the following functions for making handling of the link
data easy. However, when the conditions (32-bit data assurance execution conditions)
are not met, provide interlocks according to the example in Section 6.2.3.
• 32-bit data assurance
• Station-based block data assurance for
cyclic data
32-bit data precision is assured automatically by setting parameters so that the
following conditions 1) to 4) are satisfied.
If conditions 1) to 4) are not satisfied, a warning for 32-bit data separation is displayed
during setting with GX Developer.
1) The start device number of LB is a multiple of 20
2) The number of assigned LB points per station is a multiple of 20
3) The start device number of LW is a multiple of 2.
4) The number of assigned LW points per station is a multiple of 2.
Parameter settings for network range assignments
2) 1)
Refreshing link devices that satisfy the above conditions 1) to 4) ensures consistency
of 32-bit data.
For the send data of less than 32 bits, an interlocked program is not required if the
above conditions are satisfied.
QCPU QJ71 I/O
BR11
Floating point
: Section 6.2.1
: Section 6.2.2
4) 3) 2) 1)
QCPU QJ71
BR11
Current values, command speed, 32-bit I/O data, etc.
.
H
4) 3)
I/O QCPU QJ71
BR11
MELSECNET/H
MELSEC-Q
.
H
I/O
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