Clock Implementation - GE UR Series Instruction Manual

8.1 OVERVIEW
where: T
= the time between execution of the filter algorithm
repeat
T = time constant for the primary phase locked loop
phase
T = time constant for the frequency locked loop
frequency
The recommended time constants are 10 seconds for the time stamp phase locking, and 1000 seconds for frequency track-
ing. The time step for the integrators is 1/60 of a second, so all of the integrator gains are small.
Another new invention in the L90 relay system is the clock. Using the conventional approach to implementing a digital clock
to achieve the desired goal for phase uncertainty of 0.01 radians. A variation of the concept used in sigma delta modulation
can be used to greatly extend the effective resolution of the clock. For example, it is possible to get the effective resolution
of a 32 bit counter and a 400 GHz oscillator without much trouble.
The concept is to implement a fractional count. The concept as applied in the L90 digital current differential relay is dis-
cussed below:
The existing crystal clock and 16 bit counter are used to control both time stamping and data sampling. The counter is
loaded with a desired period, which is in effect for four data samples. Each time the period is counted out, data is sampled.
After 4 samples (1/16 of a cycle), the counter is reloaded, possibly with a new value. The new idea is implemented com-
pletely in software.
Time periods between data samples are computed as a 32 bit multiple of the period of the clock, with a 16 bit integer and a
16 fraction. Two separate 16 bit registers are used to control the clock. One register controls the integer portion of the time
period, the other is used to control the fractional portion. The integer register is used to reload the hardware counter every
four samples.
There are two possible reload values for the counter: either the value in the integer register is used directly, or one is added
to it, depending on the contents of the fraction register. The fraction register is used to carry a running total of the fractional
portion of the desired time period. Each time the hardware counter is reloaded, the fractional portion of the desired period is
added to the fractional register, occasionally generating a carry. Whenever a carry is generated, the counter reload value
for the next period is increased by one for that period only. The fractional register is never reset, even when the desired
period changes. Other clock related functions include time stamps and sequence numbers.
Phase noise analysis indicates that not many bits are needed for time stamps because of the smoothing effects of the loop
filter. Basically, a simple integer count of the number of samples is adequate. That is, a resolution of 260 microseconds in
the time stamps is adequate. Assuming a worst round trip channel delay of 4 cycles, an 8 bit counter is adequate for time
stamping. Every 1/64 of a cycle when data is sampled, an 8 bit counter should be incremented and allowed to simply roll
over to 0 after a count of 255 which should occur exactly every 4 cycles at the beginning of the cycle. Whenever a time
stamp is needed, the time stamp counter is simply read.
A message sequence number is also needed with a granularity of 1/2 cycle. A message sequence number can be simply
extracted from the 4 high order bits of the time stamp counter. Since the time stamps may or may not have any relationship
to the message sequence number in a message, both are needed.
8
An algorithm is needed to match phaselets, detect lost messages, and detect communications channel failure. Channel
failure is defined by a sequence of lost messages, where the length of the sequence is a design parameter. In any case, the
sequence should be no longer than the maximum sequence number (4 cycles) in order to be able to match up messages
when the channel is assumed to be operating normally.
A channel failure can be simply detected by a watchdog software timer which times the interval between consecutive
incoming messages. If the interval exceeds a maximum limit, channel failure is declared and the channel recovery process
is initiated.
While the channel is assumed to be operating normally, it is still possible for an occasional message to be lost, in which
case fault protection is suspended for the time period that depends on that message, and is resumed on the next occa-
sional message. A lost message is detected simply by looking at the sequence numbers of incoming messages. A lost
message will show up as a gap in the sequence.
Sequence numbers are also used to match messages for the protection computation. Whenever a complete set of current
measurements from all terminals with matching sequence numbers are available, the differential protection function is com-
puted using that set of measurements.
8-12 L90 Line Differential Relay
8 THEORY OF OPERATION

8.1.13 CLOCK IMPLEMENTATION

8.1.14 MATCHING PHASELETS
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