Figure 5-2 Clear/Hold Setting; Table 5-1 Transfer Stop - Hitachi LQE550 User Manual

(3) Transfer stop
Transfers stop depending on the states of the CPU link module and the CPU (or LPU)
module defined in Table 5-1.
State
Power off The power module is powered off, or the power is off.
CPU STOP The LADDER switch on the CPU (or LPU) module's front-
panel is set to STOP.
CPU DOWN An internal error occurred in the CPU (or LPU).
CPU reset The RESET switch on the CPU (or LPU) module's front
panel was ON.
CPU link module The internal circuit has failed.
internal error
Unable to transmit The CPU has its transfer area set to zero.
(4) Reception timeout
A reception timeout occurs in any of the following conditions:
• Any CPU (or LPU) connected to the link line has been disabled from transmission due to
any condition mentioned in item (3) in "5.1 Transfer Cycle."
• Data has been destroyed (for a consecutive period of 500 ms or longer) due to sequential
noise interference or any other effect.
• The link line cable is disconnected or has defective contact.
When a reception timeout is detected in the G-register area in a CPU (or LPU), the G-register
area is either held or cleared to zero depending on the clear/hold setting that is entered from
the personal computer.
For information on how to set hold/clear, see "4.6 Setting Module Information."
CPU1
G-register area
Area 1
Area 2
Area 3
Transmission stop

Table 5-1 Transfer Stop

Cause
CPU2
G-register area
Hold area
Area 2
Area 3
Set hold

Figure 5-2 Clear/Hold Setting

5-3
5 PROGRAMMING
Transmission Reception
Stopped Stopped
Stopped Enabled
Stopped Stopped
Stopped Stopped
Stopped Stopped
Stopped Enabled
CPU3
G-register area
Clear area
1 to zero
Area 2
Area 3
Set clear