Transmission Delay Time; Slave Module (Input) To Master Module - Mitsubishi Electric MELSEC-Q Series User Manual

8.2

Transmission Delay Time

This section describes the transmission delay time (time until data is transmitted).
8.2.1

Slave module (input) to master module

The figure below shows the time between a signal input to the slave module and the CPU module device (X) turning
on/off.
Slave module
Master module
CPU module
[Calculation formula]
1) Signal delay time of the slave module + 2) Transmission cycle time  2 + 3) Processing time on the master module
side + 4) Sequence program scan time  2 [ms]
[Calculation example]
1) Signal delay time of the slave module
Signal delay time of the slave module is 0.17ms: 0.17 [ms]
2) Transmission cycle time  2
When the transmission point is set to 1024 and the transmission speed is set to 31.3kHz: 17.1  2 = 34.2 [ms]
3) Processing time on the master module side
Processing time on the master module side = Transmission speed clock width  16
When the transmission speed is set to 31.3kHz: (1  31.3k)  16 = 0.511 [ms]
4) Sequence program scan time  2
Set the sequence program scan time to 5ms: 5  2 = 10 [ms]
Therefore, the transmission delay time is 0.17 + 34.2 + 0.511 + 10 = 44.88 [ms].
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Input
1) Signal delay time on the slave module
2) One to 2 transmission cycle
times
3) Processing time on the
master module side
4) Sequence program scan
time