Master Module To Slave Module (Output) - Mitsubishi Electric MELSEC-Q Series User Manual

CHAPTER 8 TRANSMISSION TIME
8.2.2

Master module to slave module (output)

The figure below shows the time between the CPU module device (Y) turning on/off and a signal output from the slave
module turning on/off.
Output
Slave module
4) Signal delay time on the slave module
3) One to 2 transmission cycle
times
Master module
2) Processing time on the
master module side
1) Sequence program scan
CPU module
time
[Calculation formula]
1) Sequence program scan time + 2) Processing time on the master module side + 3) Transmission cycle time  2 + 4)
Signal delay time of the slave module [ms]
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[Calculation example]
1) Sequence program scan time
Set the sequence program scan time to 5ms: : 5 [ms]
2) Processing time on the master module side
Processing time on the master module side = Transmission speed clock width  16
When the transmission speed is set to 31.3kHz: (1  31.3k)  16 = 0.511 [ms]
3) Transmission cycle time  2
When the transmission point is set to 1024 and the transmission speed is set to 31.3kHz: 17.1  2 = 34.2 [ms]
4) Signal delay time of the slave module
Signal delay time of the slave module is 0.01ms : 0.01 [ms]
Therefore, the transmission delay time is 5 + 0.511 + 34.2 + 0.01 = 39.72 [ms].
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