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Asus AAEON NanoCOM-WHU User Manual

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NanoCOM-WHU
COM Express Module
st
User's Manual 1
Ed
Last Updated: July 29, 2020

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Summary of Contents for Asus AAEON NanoCOM-WHU

  • Page 1 NanoCOM-WHU COM Express Module User’s Manual 1 Last Updated: July 29, 2020...
  • Page 2 Copyright Notice This document is copyrighted, 2020. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel® and Celeron® are registered trademarks of Intel Corporation ⚫ Intel Core™ is a trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity NanoCOM-WHU ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions, Jumpers and Connectors ............... 5 Row A/B Connector Pin Definitions ..............7 Chapter 3 - AMI BIOS Setup ....................12 System Test and Initialization ................
  • Page 12 3.5.4 Digital IO Port Configuration ..............38 3.5.5 Legacy Logical Devices Configuration ..........39 3.5.5.1 [*Active*] Serial Port 1 ............... 40 3.5.5.2 [*Active*] Serial Port 2 ...............41 3.5.6 Serial Port Console Redirection .............. 42 3.5.6.1 Legacy Console Redirection Settings..........43 Setup Submenu: Security ..................

  • Page 13: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 14: Specifications

    Specifications System Form Factor COM Express Mini size, 84mm x 55mm 8th Generation Intel® Core™ ULT Series Processors CPU Frequency — Chipset Onboard 8th Generation Intel® Core™ SoC Memory Type Onboard DDR4-2400/2133, non ECC support. Max. Memory Capacity Up to 8GB BIOS AMI BIOS, Legacy free BIOS Wake on LAN...
  • Page 15 Display VGA/LCD Controller Intel® UHD Graphics 620 / 610 Video Output eDP, DDI x 1 LVDS Interface — Ethernet Intel® I219 GbE x 1 Audio HD Audio x 1 USB port USB 3.2 Gen 2 x 2 USB 2.0 x 8 Serial Port 2-wire UART x 2 (TX/RX) HDD Interface...

  • Page 16: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 17: Dimensions, Jumpers And Connectors

    Dimensions, Jumpers and Connectors Chapter 2 – Hardware Information...
  • Page 18 Chapter 2 – Hardware Information...

  • Page 19: Row A/B Connector Pin Definitions

    Row A/B Connector Pin Definitions Row A Row B GND (FIXED) GND (FIXED) GBE0_MDI3- GBE0_ACT# GBE0_MDI3+ LPC_FRAME# GBE0_LINK100# LPC_AD0 GBE0_LINK1000# LPC_AD1 GBE0_MDI2- LPC_AD2 GBE0_MDI2+ LPC_AD3 GBE0_LINK# GBE0_MDI1- GBE0_MDI1+ LPC_CLK GND (FIXED) GND (FIXED) GBE0_MDI0- PWRBTN# GBE0_MDI0+ SMB_CK SMB_DAT SUS_S3# SMB_ALERT# SATA0_TX+ SATA1_TX+ SATA0_TX-...
  • Page 20 Row A Row B USB3_RXN1 USB3_TXN1 USB3_RXP1 USB3_TXP1 BATLOW# ATA_ACT# AC_SYNC AC_SDIN1 AC_RST# AC_SDIN0 GND (FIXED) GND (FIXED) AC_BITCLK SPKR AC_SDOUT I2C_CK BIOS_DIS0# I2C_DAT THRMTRIP# THRM# USB6- USB7- USB6+ USB7+ USB_6_7_OC# USB_4_5_OC# USB4- USB5- USB4+ USB5+ GND (FIXED) GND (FIXED) USB2- USB3- USB2+...
  • Page 21 Row A Row B GND (FIXED) GND (FIXED) N.C. N.C. N.C. N.C. GPI0 GPO1 N.C. N.C. N.C. N.C. GPO2 PCIE_TX3+ PCIE_RX3+ PCIE_TX3- PCIE_RX3- GND (FIXED) GND (FIXED) PCIE_TX2+ PCIE_RX2+ PCIE_TX2- PCIE_RX2- GPI1 GPO3 PCIE_TX1+ PCIE_RX1+ PCIE_TX1- PCIE_RX1- WAKE0# GPI2 WAKE1# PCIE_TX0+ PCIE_RX0+ PCIE_TX0-...
  • Page 22 Row A Row B EDP_VDD_EN N.C. N.C. N.C. N.C. EDP_BKLT_EN GND (FIXED) GND (FIXED) EDP_TXP3 DDI0_PAIR3+ EDP_TXN3 DDI0_PAIR3- EDP_AUXP EDP_BKLTCTL EDP_AUXN VCC_5V_SBY GPI3 VCC_5V_SBY N.C. VCC_5V_SBY EDP_HDP VCC_5V_SBY PCIE0_CK_REF+ BISO_DIS1# PCIE0_CK_REF- DDI0_HPD GND (FIXED) GND (FIXED) SPI_POWER N.C. SPI_MISO N.C. GPO0 N.C.
  • Page 23 Row A Row B A101 RS2_TX B101 FAN_PWMOUT A102 RS2_RX B102 FAN_TACHIN A103 LID# B103 SLEEP# A104 VCC_12V B104 VCC_12V A105 VCC_12V B105 VCC_12V A106 VCC_12V B106 VCC_12V A107 VCC_12V B107 VCC_12V A108 VCC_12V B108 VCC_12V A109 VCC_12V B109 VCC_12V A110 GND (FIXED) B110...

  • Page 24: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 25: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 26: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 27: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 28: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 29: Graphics Configuration

    3.4.1 Graphics Configuration Options Summary Skip Scanning of Enable External Gfx Card Disable Optimal Default, Failsafe Default If Enable, it will not scan for External Gfx Card on PEG and PCH PCIE Ports. Primary Display Auto Optimal Default, Failsafe Default IGFS Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.
  • Page 30 Options Summary DVMT Pre-Allocated Optimal Default, Failsafe Default 32M/F7 Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. DVMT Total Gfx 128M 256M Optimal Default, Failsafe Default Chapter 3 – AMI BIOS Setup...

  • Page 31: Cpu Configuration

    3.4.2 CPU Configuration Options Summary Active Processor Optimal Default, Failsafe Default Cores Number of cores to enable in each processor package. Hyper-Threading Disabled Enabled Optimal Default, Failsafe Default Enabled or Disabled Hyper-Threading Technology. Intel Trusted Disabled Optimal Default, Failsafe Default Execution Enabled Technology...
  • Page 32 Options Summary Intel® SpeedStep™ Disabled Enabled Optimal Default, Failsafe Default Allows more than two frequency ranges to be supported. Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Enable/Disable processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled).

  • Page 33: Memory Configuration

    3.4.3 Memory Configuration Chapter 3 – AMI BIOS Setup...

  • Page 34: On-Module H/W Monitor

    3.4.4 On-Module H/W Monitor Chapter 3 – AMI BIOS Setup...

  • Page 35: Fan 1 Mode Configuration

    3.4.4.1 Fan 1 Mode Configuration Options Summary FAN 1 Full Mode Optimal Default, Failsafe Default Manual Mode by PWM Auto Mode by PWM Choose the mode for FAN 1. PWM signal Non-inverting Optimal Default, Failsafe Default Inverting Select output PWM of inverting or non-inverting signal. Chapter 3 –...

  • Page 36: Pch-Fw Configuration

    3.4.5 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 37: Firmware Update Configuration

    3.4.5.1 Firmware Update Configuration Options Summary Me FW Image Enabled Re-Flash Disabled Optimal Default, Failsafe Default Enable/Disable Me FW Image Re-Flash function. Local FW Update Enabled Optimal Default, Failsafe Default Disabled Options for Local FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 38: On-Module Configuration

    3.4.6 On-Module Configuration Options Summary Battery Disabled Optimal Default, Failsafe Default Management One Battery Enable to support battery in ACPI OS by I2C_CK, I2C_DAT(B33,B34) EC-SMB-HC Enabled Support Disabled Optimal Default, Failsafe Default SMBus Host Controller Interface via Embedded Controller. Chapter 3 – AMI BIOS Setup...

  • Page 39: Power Management

    3.4.7 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode. Restore AC Power Last State Loss Always On Always Off Optimal Default, Failsafe Default IO Restore AC Power Loss. RTC wake system Disabled Optimal Default, Failsafe Default from S5.

  • Page 40: Aaeon Bios Robot

    3.4.8 AAEON BIOS Robot Options Summary Sends watch dog Disabled Optimal Default, Failsafe Default before BIOS POST. Enabled Enabled - Robot set Watch Dog Timer (WDT) right after power on, before BIOS start POST process. And then Robot will clear WDT on completion of POST. WDT will reset system automatically if it is not cleared before its timer counts down to zero.
  • Page 41 Options Summary Delayed POST (PEI Disabled Optimal Default, Failsafe Default phase) Enabled Enabled – Robot holds BIOS from starting POST, right after power. This allows BIOS POST to start with stable power or start after system is physically warmed-up. Note: Robot does this before ‘Sends watch dog’. Delayed POST (DXE Disabled Optimal Default, Failsafe Default...

  • Page 42: Device Detecting Configuration

    3.4.8.1 Device Detecting Configuration Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Soft or hard reset Soft Optimal Default, Failsafe Default Hard Select reset type robot should send on each boot. Retry-Count Optimal Default, Failsafe Default Fill retry counter here.
  • Page 43 3.4.8.1.1 Device #1~5 Detecting Configuration Options Summary Interface Disabled Optimal Default, Failsafe Default SMBUS Legacy I/O Super I/O MMIO Select interface robot should use to communicate with device. Note: This menu is the same for all Devices #1 thru #5. Chapter 3 –...

  • Page 44: Setup Submenu: System I/O

    Setup Submenu: System I/O Chapter 3 – AMI BIOS Setup...

  • Page 45: Pci Express Configuration

    3.5.1 PCI Express Configuration Options Summary PCIE_0~3 As Four x1 Optimal Default, Failsafe Default Configuration As one x2 and two x1 As two x2 As one x4 PCIE Controller Selection. Chapter 3 – AMI BIOS Setup...

  • Page 46: Pcie_# Configuration

    3.5.1.1 PCIE_# Configuration Options Summary PCIE_N Disabled Enabled Optimal Default, Failsafe Default Control the PCI Express Root Port. PCIe Speed Auto Optimal Default, Failsafe Default Gen1 Gen2 Gen3 Configure PCIe Speed. Note: This menu is the same for PCIE_0, PCIE_1, PCIE_2, and PCIE_3. Chapter 3 –...

  • Page 47: Storage Configuration

    3.5.2 Storage Configuration Options Summary eMMC 5.0 Disabled Controller Enabled Optimal Default, Failsafe Default Enable or Disable SCS eMMC 5.0 Controller. eMMC 5.0 HS400 Disabled Mode Enabled Optimal Default, Failsafe Default Enable or Disable SCS eMMC HS400 Mode. Driver Strength 33 Ohm 40 Ohm Optimal Default, Failsafe Default...
  • Page 48 Options Summary SATA Mode AHCI Optimal Default, Failsafe Default Selection Intel RST Premium with Intel Optane System Acceleration Determines how SATA controller(s) operate. SATA Port 0/1 Configuration Port 0/1 Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port 0/1 Hot Plug Disabled Optimal Default, Failsafe Default...

  • Page 49: Hd Audio Configuration

    3.5.3 HD Audio Configuration Options Summary HD Audio Disabled Enabled Optimal Default, Failsafe Default Control Detection of the HD-Audio device. Disabled: HD-Audio will be unconditionally disabled. Enabled: HD-Audio will be unconditionally disabled. Chapter 3 – AMI BIOS Setup...

  • Page 50: Digital Io Port Configuration

    3.5.4 Digital IO Port Configuration Options Summary IO Type Output Optimal Default, Failsafe Default Input Set IO as Input or Output IO Data High Optimal Default, Failsafe Default Set is output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 51: Legacy Logical Devices Configuration

    3.5.5 Legacy Logical Devices Configuration Chapter 3 – AMI BIOS Setup...

  • Page 52: Active*] Serial Port 1

    3.5.5.1 [*Active*] Serial Port 1 Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4; DMA; IO=2C8h; IRQ=11; DMA Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 53: Active*] Serial Port 2

    3.5.5.2 [*Active*] Serial Port 2 Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3; DMA; IO=2D8h; IRQ=10; DMA Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 54: Serial Port Console Redirection

    3.5.6 Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default, Failsafe Default (COM0) Enabled Console Redirection Enable or Disable. Optimal Default, Failsafe Default Console Redirection Disabled Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup...

  • Page 55: Legacy Console Redirection Settings

    3.5.6.1 Legacy Console Redirection Settings Options Summary Redirection COM COM0 Optimal Default, Failsafe Default Port Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages Resolution 80x24 Optimal Default, Failsafe Default 80x25 On Legacy OS, the Number of Rows and Columns supported redirection. Redirect After POST Always Enable Optimal Default, Failsafe Default Bootloader...

  • Page 56: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 57: Secure Boot

    3.6.1 Secure Boot Options Summary Secure Boot Disable Optimal Default, Failsafe Default Enable Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System mode is in User mode. Changing the mode requires platform reset. Secure Boot Mode Standard Optimal Default, Failsafe Default Custom...

  • Page 58: Key Management

    3.6.2 Key Management Options Summary Factory Key Disabled Optimal Default, Failsafe Default Provision Enabled Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode. Restore Factory Press ‘Yes’ to install factory default Keys keys Force System to User Mode.
  • Page 59 Secure Boot Variable | Size | Keys# | Key Source Platform Key (PK) | 0 | 0 | No Key Update Enroll Factory Defaults or load certificates from a file: 1.Public key Certificate: a) EFI_SIGNATURE_LIST b) EFI_CERT_X509 (DER) c) EFI_CERT_RSA2048 (bin) d) EFI_CERT_SHAXXX 2.Authenticated UEFI Variable 3.EFI PE/COFF Image (SHA256)
  • Page 60 Secure Boot Variable | Size | Keys# | Key Source Forbidden Signatures | 0 | 0 | No Key Update Enroll Factory Defaults or load certificates from a file: Append 1.Public key Certificate: a)EFI_SIGNATURE_LIST b)EFI_CERT_X509 (DER) c)EFI_CERT_RSA2048 (bin) d)EFI_CERT_SHAXXX 2.Authenticated UEFI Variable 3.EFI PE/COFF Image(SHA256) Key Source: Factory, External, Mixed...

  • Page 61: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enables or disables Quiet Boot option. PXE Boot Disabled Optimal Default, Failsafe Default UEFI Controls the execution of UEFI and Legacy Network OpROM. Chapter 3 – AMI BIOS Setup...

  • Page 62: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 63: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 64: Driver Download And Installation

    Driver Download and Installation Drivers for the NanoCOM-WHU can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/com-express-modules-nanocom-whu Download the driver(s) you need and extract the zip. Then, follow the steps below to install the drivers. Step 1 –...
  • Page 65 Step 4 – Install Audio Drivers Open the Realtek Audio R2.82 folder Run the 0009-64bit_Win7_Win8_Win81_Win10_R282.exe file in the folder Follow the instructions Drivers will be installed automatically Step 5 – Install Intel Management Engine Firmware Open the Intel(R) Management Engine Firmware 1910.12.0.1239 folder Run the MEISetup.exe file in the folder Follow the instructions Drivers will be installed automatically...

  • Page 66: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 67: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1: Embedded BRAM relative register table Default Value Note Index 0x284(Note1) BRAM Index Register Data 0x285(Note2) BRAM Data Register Logical Device Number 0xA8(Note3) Watch dog Logical Device Number Function and Device Number 0x00(Note4) Watch dog Function/Device Number Table 2: Watchdog relative register table Option Register BitNum...
  • Page 68 ************************************************************************************ // Embedded BRAM relative definition (Please reference to Table 1) #define byte EcBRAMIndex //This parameter is represented from Note1 #define byte EcBRAMData //This parameter is represented from Note2 #define byte BRAMLDNReg //This parameter is represented from Note3 #define byte BRAMFnDataReg //This parameter is represented from Note4 #define void EcBRAMWriteByte(byte Offset, byte Value);...
  • Page 69 ************************************************************************************ Main VOID // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 70 ************************************************************************************ // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable( // Procedure : AaeonWDTConfig AaeonWDTConfig () VOID // Disable WDT counting WDTEnableDisable( // WDT relative parameter setting WDTParameterSetting(); WDTEnableDisable(byte Value) VOID ECBRAMWriteByte(TimerReg , Value); WDTParameterSetting() VOID Byte TempByte; // Watchdog Timer counter setting ECBRAMWriteByte(TimerReg , TimerVal);...
  • Page 71 ************************************************************************************ ECBRAMWriteByte(byte OPReg, byte OPBit, byte Value) VOID IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x13 + OPReg); IOWriteByte(EcBRAMData, Value); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x30); //Write start ECBRAMReadByte(byte OPReg) Byte IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x10);...

  • Page 72: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 73: I/O Address Map

    I/O Address Map Appendix B – I/O Information...

  • Page 74: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 75: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 76 Appendix B – I/O Information...
  • Page 77 Appendix B – I/O Information...
  • Page 78 Appendix B – I/O Information...
  • Page 79 Appendix B – I/O Information...
  • Page 80 Appendix B – I/O Information...
  • Page 81 Appendix B – I/O Information...
  • Page 82 Appendix B – I/O Information...
  • Page 83 Appendix B – I/O Information...

  • Page 84: Appendix C - Programming Digital I/O

    Appendix C Appendix C – Programming Digital I/O...

  • Page 85: Dio Programming

    DIO Programming NanoCOM-WHU utilizes an AAEON chipset as its Digital I/O controller. Below are the procedures to complete its configuration which you can use to develop a customized program to fit your application. Appendix C –Programming Digital I/O...

  • Page 86: Digital I/O Register

    Digital I/O Register Table 1: Embedded BRAM relative register table Default Value Note Index 0x284(Note1) BRAM Index Register Data 0x285(Note2) BRAM Data Register Logical Device Number 0xA2(Note3) Watch dog Logical Device Number IO Direction DIO Input/Output Function/Device 0x00(Note4) Function and Device Number Number IO Value/Status DIO Output Data Function/Device...

  • Page 87: Digital I/O Sample Program

    Digital I/O Sample Program ************************************************************************************ // Embedded BRAM relative definition (Please reference to Table 1) #define byte EcBRAMIndex //This parameter is represented from Note1 #define byte EcBRAMData //This parameter is represented from Note2 #define byte BRAMLDNReg //This parameter is represented from Note3 #define byte BRAMFnData0Reg //This parameter is represented from Note4 #define byte BRAMFnData1Reg //This parameter is represented from Note5 #define void EcBRAMWriteByte(byte Offset, byte Value);...
  • Page 88 ************************************************************************************ Main VOID Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DIO0ToDIO7Reg, DIO3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 89 ************************************************************************************ AaeonReadPinStatus(byte OptionReg, byte BitNum) Boolean Byte TempByte; TempByte = ECBRAMReadByte(BRAMFnData1Reg, OptionReg); If (TempByte & BitNum == 0) Return 0; Return 1; AaeonSetOutputLevel(byte OptionReg, byte BitNum, byte Value) VOID Byte TempByte; TempByte = ECBRAMReadByte(BRAMFnData1Reg, OptionReg); TempByte |= (Value << BitNum); ECBRAMWriteByte(OptionReg, BitNum, Value);...
  • Page 90 ************************************************************************************ ECBRAMWriteByte(byte OPReg, byte OPBit, byte Value) VOID IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x13 + OPReg); IOWriteByte(EcBRAMData, Value); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x30); //Write start ECBRAMReadByte(byte FnDataReg, byte OPReg) Byte IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, FnDataReg); IOWriteByte(EcBRAMIndex, 0x12);...

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