Functional Block Diagram - Fujitsu 5GRUDB3 User Manual

RU Hardware Feature

Functional Block Diagram

2.6
Functional Block Diagram
The following figure shows a functional diagram of the RU.
DPDC#A
PL
Opt Module
Serdes
(10G)
PHY
SRAM
MAC
PS
I2C
EEPROM
QSPI
QSPI-FLASH MPU
(Multi-
Core)
Memory
DDR-JF
Controller
DDR4
Work Memory
+ECC
RJ45
LAN-PHY
CN
RGMII
1000BASE-T
LED
AISG
PTP
Device
Figure 5
Functional Diagram
Table 14
Description of Function Block
Function Block
DPDC#A
·
Issue 1.1, May 2021
Release 1.0
TRX#1
iFFT
CFR
DPD
FFT Hi Speed
Rx
RACH DDC
PCI-e
Bus
Controller
DPDC#B
TRX#2
CFR
DPD
Rx
DDC
SPI +53V, +12V
PS
DPRF#A
+53V, +12V
DPRF#B
+12V
DPDC
+24V
DPDC
CLK
(AISG)
Jitter
Cleaner
PS
PPL
HOT&SWAP
-48V
EMI-Fil
Surge
Name
Digital Pre-Distortion
Central unit#A
n70n66-RF#A
40W
TXCONV PA
RF-IC
JESD
2T2R
n70
RXCONV
RF-SW
RF-IC
60W
2T2R
TXCONV PA
n66
RF-SW
n70n66-RF#B
40W
PA
TXCONV
RF-IC
JESD
2T2R
n70
RXCONV
RF-SW
RF-IC
60W
2T2R
TXCONV PA
n66
RF-SW
Function
▪ DPDC#A monitors and controls each interface in the RU by LLB. It
has a Digital Pre-Distortion (DPD) and Crest Factor Reduction
(CFR) control function for PA of n70n66-RF#A.
▪ The eCPRI block in the LLB has a Serdes interface with the optical
module and a PHY/MAC unit that constructs the frame format of
the C/U/S/M-Plane.
▪ The iFFT/FFT block performs IQ conversion/inverse conversion of
the uplink ad downlink U-planes.
▪ The RACH Block is a processing function for the random access
channel.
DUP
ANT
#A
RVS#A
ANT
#C
RVS#C
ANT
#B
RVS#B
ANT
#D
RVS#D
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