Ieee1394 Module (F3 Sub) Block Diagram - Panasonic AJ-SD93P/E Service Manual

IEEE1394 MODULE (F3 SUB) BLOCK DIAGRAM

P1701
CFNRESET
FROM/TO (F3)
DPROC P1701
BOARD
CF DATA
CFCLK
UPADR (1-15)
UPDAT (0-15)
NPOWERDOWN
NUPCS, NUPRD,
NUPWAIT, NUPBHW,
NUPBLW, BCLK,
NUPINT
P1701
DVRECDAT (0-7)
DVPBDAT (0-7)
DVPBFRM,
DVPBSSP,
DVREFFRM,
DVRECFRM,
DVRECSSP
P1701
NRESET
P10101
34A
IC10501 (5)
P10101
32B
33B
6-12B,
14-21B
5-12A,
14-21A
2A, 5B,
22A/B,
23A/B,
24A/B
P10101
40A-48A
41B-48B
37-39A
38,39B
IC10707 (4)
P10101
RESET
2B
IC10705,
10707 (7)
RESET
GEN. &
GATE
8 PHY DATA BUS
2 PYH CONTROL BUS
CLK
X10401 (4)
25MHz
CLK GEN.
FPGA
DUEL
X10201, IC10201 (2)
1.8MHz
CLK
GEN.
IC10601 (6)
RAM ADRS 13
RAM CONTROLL
SDRAM
RAM DATA 16
IC10401 (4)
P10301
TPB-, TPB+
TPA-, TPA+
PHY
P10302
TPB-, TPB+
TPA-, TPA+
IEEE1394
CONNECTOR
1, 2
4, 5
1, 2
4, 5