Page 1 User’s Manual µ PD789426, 789436, 789446, 789456 Subseries 8-Bit Single-Chip Microcontrollers µ µ PD789425 PD789445 µ µ PD789426 PD789446 µ µ PD789435 PD789455 µ µ PD789436 PD789456 µ µ PD78F9436 PD78F9456 Document No. U15075EJ2V1UD00 (2nd edition) Date Published August 2005 N CP(K) ©...
Page 2 [MEMO] User’s Manual U15075EJ2V1UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 FIP and EEPROM are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
Page 5 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 6 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 [MEMO] User’s Manual U15075EJ2V1UD...
Page 8 INTRODUCTION Target Readers This manual is intended to give user engineers an understanding of the functions of µ PD789426, 789436, 789446, and 789456 Subseries to design and develop its application systems and programs. Target products: µ µ • PD789426 Subseries: PD789425, 789426 µ...
Page 9 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 10 Document No. SEMICONDUCTOR SELECTION GUIDE -Products and Packages- X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 11: Table Of Contents
CONTENTS CHAPTER 1 GENERAL .......................... 25 Features ............................25 Applications ..........................25 Ordering Information ......................... 26 Pin Configuration (Top View) ....................27 µ 1.4.1 Pin configuration of PD789426, 789436 Subseries (Top view) ........... 27 µ 1.4.2 Pin configuration of PD789446, 789456 Subseries (Top view) ........... 28 78K/0S Series Lineup ........................
Page 12 CHAPTER 3 CPU ARCHITECTURE ......................46 Memory Space..........................46 3.1.1 Internal program memory space ....................52 3.1.2 Internal data memory (internal high-speed RAM) space ............... 53 3.1.3 Special function register (SFR) area ..................... 53 3.1.4 Data memory addressing ......................54 Processor Registers ........................60 3.2.1 Control registers..........................
Page 13 Clock Generator Configuration ....................102 Registers Controlling Clock Generator .................104 System Clock Oscillators......................108 5.4.1 Main system clock oscillator (crystal/ceramic oscillation)............108 5.4.2 Main system clock oscillator (RC oscillation) (mask option) ............109 5.4.3 Subsystem clock oscillator ......................109 5.4.4 Example of incorrect resonator connection ................. 110 5.4.5 Divider circuit ..........................
Page 14 8.4.1 Operation as watch timer ......................180 8.4.2 Operation as interval timer ......................180 CHAPTER 9 WATCHDOG TIMER .......................182 Watchdog Timer Functions.....................182 Watchdog Timer Configuration ....................183 Watchdog Timer Control Registers..................184 Watchdog Timer Operation.....................186 9.4.1 Operation as watchdog timer ...................... 186 9.4.2 Operation as interval timer ......................
Page 15 13.4 Setting LCD Controller/Driver....................257 13.5 LCD Display Data Memory ......................257 13.6 Common and Segment Signals ....................258 13.7 Display Modes..........................260 13.7.1 Three-time slot display example ....................260 13.7.2 Four-time slot display example ....................263 13.8 Supplying LCD Drive Voltages V , and V .............266 CHAPTER 14 INTERRUPT FUNCTIONS ....................267 14.1 Interrupt Function Types......................267...
Page 16 19.3 Instructions Listed by Addressing Type ................312 CHAPTER 20 ELECTRICAL SPECIFICATIONS.................315 CHAPTER 21 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES)....................333 CHAPTER 22 PACKAGE DRAWINGS....................335 CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS............337 APPENDIX A DEVELOPMENT TOOLS....................340 Software Package ........................342 Language Processing Software .....................342 Control Software ........................343 Flash Memory Writing Tools ....................343 Debugging Tools (Hardware)....................344...
Page 17 LIST OF FIGURES (1/6) Figure No. Title Page Pin Input/Output Circuits..........................45 µ Memory Map ( PD789425, 789435) .......................46 µ Memory Map ( PD789426, 789436) .......................47 µ Memory Map ( PD78F9436) ...........................48 µ Memory Map ( PD789445, 789455) .......................49 µ Memory Map ( PD789446, 789456) .......................50 µ...
Page 18 LIST OF FIGURES (2/6) Figure No. Title Page 4-19 Format of Pull-Up Resistor Option Register 0....................97 4-20 Format of Pull-Up Resistor Option Register B2 ....................98 4-21 Format of Pull-Up Resistor Option Register B3 ....................98 4-22 Format of Pull-Up Resistor Option Register B7 ....................99 4-23 Format of Pull-Up Resistor Option Register B8 ....................99 4-24...
Page 19 LIST OF FIGURES (3/6) Figure No. Title Page Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) ..........152 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) ........152 7-10 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)........153 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N <...
Page 20 LIST OF FIGURES (4/6) Figure No. Title Page 10-7 How to Reduce Current Consumption in Standby Mode ................197 10-8 Conversion Result Read Timing (If Conversion Result Is Undefined)............198 10-9 Conversion Result Read Timing (If Conversion Result Is Normal) ..............198 10-10 Analog Input Pin Treatment ...........................199 10-11 A/D Conversion End Interrupt Request Generation Timing ................200...
Page 21 LIST OF FIGURES (5/6) Figure No. Title Page 13-7 Voltages and Phases of Common and Segment Signals ................259 13-8 Three-Time Slot LCD Display Pattern and Electrode Connections..............260 13-9 Example of Connecting Three-Time Slot LCD Panel..................261 13-10 Three-Time Slot LCD Drive Waveform Examples ..................262 13-11 Four-Time Slot LCD Display Pattern and Electrode Connections..............263 13-12...
Page 22 LIST OF FIGURES (6/6) Figure No. Title Page 17-1 Environment for Writing Program to Flash Memory ..................295 17-2 Communication Mode Selection Format......................296 17-3 Example of Connection with Dedicated Flash Programmer................297 17-4 Pin Connection Example.........................299 17-5 Signal Conflict (Serial Interface Input Pin) .....................300 17-6 Malfunction of Another Device........................300 17-7...
Page 23 LIST OF TABLES (1/2) Table No. Title Page Types of Pin Input/Output Circuits ........................44 Internal ROM Capacity ............................52 Vector Table ..............................52 LCD Display RAM Capacity..........................53 Special Function Register List .........................65 Port Functions ..............................78 Configuration of Port............................79 Port Mode Register and Output Latch Settings When Using Alternate Functions ...........97 Configuration of Clock Generator ........................102 Maximum Time Required for Switching CPU Clock (When Crystal/Ceramic Oscillation Is Selected) ...116 Maximum Time Required for Switching CPU Clock (When RC Oscillation Is Selected)........116...
Page 24 LIST OF TABLES (2/2) Table No. Title Page 11-1 Configuration of 10-Bit A/D Converter ......................201 12-1 Configuration of Serial Interface 20 .......................214 12-2 Serial Interface 20 Operating Mode Settings ....................220 12-3 Example of Relationships Between System Clock and Baud Rate..............223 12-4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ..224 12-5...
Page 25: Chapter 1 General
CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Program Memory Data Memory Internal High-Speed LCD Display RAM Part Number µ PD789425, 789435 Mask ROM 8 KB 512 bytes 5 bytes µ PD789426, 789436 16 KB µ PD78F9436 Flash memory 16 KB µ...
Page 26: Ordering Information
CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package Internal ROM µ 64-pin plastic TQFP (fine pitch) (12 × 12) PD789425GK-×××-9ET Mask ROM µ 64-pin plastic TQFP (fine pitch) (12 × 12) PD789426GK-×××-9ET Mask ROM µ 64-pin plastic TQFP (fine pitch) (12 × 12) PD789435GK-×××-9ET Mask ROM µ...
Page 27: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) µ 1.4.1 Pin configuration of PD789426, 789436 Subseries (Top view) • 64-pin plastic TQFP (fine pitch) (12 × 12) µ µ µ PD789425GK-×××-9ET PD789425GK-×××-9ET-A PD78F9436GK-9ET µ µ µ PD789426GK-×××-9ET PD789426GK-×××-9ET-A PD78F9436GK-9ET-A µ µ...
Page 28 CHAPTER 1 GENERAL µ 1.4.2 Pin configuration of PD789446, 789456 Subseries (Top view) • 64-pin plastic TQFP (fine pitch) (12 × 12) µ µ µ PD789445GK-×××-9ET PD789445GK-×××-9ET-A PD78F9456GK-9ET µ µ µ PD789446GK-×××-9ET PD789446GK-×××-9ET-A PD78F9456GK-9ET-A µ µ PD789455GK-×××-9ET PD789455GK-×××-9ET-A µ µ PD789456GK-×××-9ET PD789456GK-×××-9ET-A •...
Page 29 CHAPTER 1 GENERAL Pin Name Note 1 ANI0 to ANI5: Analog input P80, P81 Port 8 Note 1 ASCK20: Asynchronous serial input P90 to P97 Port 9 Analog power supply RESET: Reset Analog ground RxD20: Receive data BZO90: Buzzer output SS20: Serial chip select Note 2...
Page 30: 0S Series Lineup
CHAPTER 1 GENERAL 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications µ...
Page 31 CHAPTER 1 GENERAL The major functional differences between the subseries are listed below. Series for General-purpose applications and LCD drive Function Timer 8-Bit 10-Bit Serial Remarks Capacity Interface 8-Bit 16-Bit Watch WDT MIN. (Bytes) Subseries Name Value µ − − −...
Page 32 CHAPTER 1 GENERAL Series for ASSP Function Timer 8-Bit 10-Bit Serial Remarks Capacity Interface 8-Bit 16-Bit Watch WDT MIN. (Bytes) Value Subseries Name µ − − − − − PD789800 8 KB 2 ch 1 ch 2 ch 4.0 V (USB: 1 ch) µ...
Page 33: Block Diagram
CHAPTER 1 GENERAL 1.6 Block Diagram µ 1.6.1 Block diagram of PD789426, 789436 Subseries TO50/TMI60/ 8-bit Port 0 P00 to P03 Cascaded timer 50 16-bit timer/ TO60/P32 8-bit event Port 1 P10, P11 TO61/P33 timer/event counter counter 60 TMI60/TO50/ P20 to P26 Port 2 TO90/P26 CPT90/P30...
Page 34 CHAPTER 1 GENERAL µ 1.6.2 Block diagram of PD789446, 789456 Subseries TO50/TMI60/ 8-bit Port 0 P00 to P03 Cascaded timer 50 16-bit timer/ TO60/P32 8-bit event Port 1 P10, P11 TO61/P33 timer/event counter counter 60 TMI60/TO50/ Port 2 P20 to P26 TO90/P26 CPT90/P30 16-bit timer 90...
Page 35: Overview Of Functions
CHAPTER 1 GENERAL 1.7 Overview of Functions µ µ µ µ µ µ PD789425, PD789426, PD78F9436 PD789445, PD789446, PD78F9456 Item 789435 789436 789455 789456 Internal memory Mask ROM Flash Mask ROM Flash memory memory 12 KB 16 KB 12 KB 16 KB High-speed RAM 512 bytes...
Page 36 CHAPTER 1 GENERAL An outline of the timer is shown below. 16-Bit 8–Bit 8-Bit Watch Timer Watchdog Timer Timer 50 Timer 60 Timer Note 1 Note 2 Operation Interval timer – 1 channel 1 channel 1 channel 1 channel mode External event –...
Page 37 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions Port pins (1/2) Pin Name Function After Reset Alternate Function P00 to P03 Port 0. Input KR0 to KR3 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00).
Page 38: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS Port pins (2/2) Pin Name Function After Reset Alternate Function − Note P80, P81 Port 8. Input 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register B8 (PUB8).
Page 39 CHAPTER 2 PIN FUNCTIONS Non-port pins Pin Name Function After Reset Alternate Function External interrupt input for which the valid edge (rising edge, INTP0 Input Input P30/CPT90 falling edge, or both rising and falling edges) can be specified INTP1 P31/TO50/TMI60 INTP2 P32/TO60 INTP3...
Page 40: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port. In addition, these pins enable key return signal detection. Port 0 can be specified in the following operation modes in 1-bit units. Port mode These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0).
Page 41: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set according to the functions to be used. For the details of the setting, refer to Table 12-2 Settings of Serial Interface 20 Operating Mode.
Page 42: P70 To P72 (Port 7)
CHAPTER 2 PIN FUNCTIONS 2.2.7 P70 to P72 (Port 7) These pins constitute a 3-bit I/O port. Port 7 can be set in the input or output mode in 1-bit units by port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register B7 (PUB7) in port units.
Page 43: Xt1, Xt2
CHAPTER 2 PIN FUNCTIONS 2.2.17 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation. To supply an external clock, input the clock to XT1 and input the inverted signal to XT2. 2.2.18 V This is the positive power supply pin. 2.2.19 V This is the ground pin.
Page 44: Pin Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Figure 2-1. Table 2-1.
Page 45: Pin Input/Output Circuits
CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuits Type 2 Type 13-V IN/OUT Output data N-ch Output disable Input enable Schmitt-triggered input with hysteresis characteristics Middle-voltage input buffer Type 5-A Type 13-W Pull-up resistor Pull-up P-ch (mask option) enable IN/OUT Output data Data...
Page 46: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space µ PD789426, 789436, 789446, and 789456 Subseries can access 64 KB of memory space. Figures 3-1 through 3-6 show the memory maps. µ Figure 3-1. Memory Map ( PD789425, 789435) FFFFH Special function registers 256 ×...
Page 47: Memory Map ( Μ Pd789426, 789436)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD789426, 789436) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 × 4 bits Data FA00H memory space...
Page 48: Pd78F9436)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD78F9436) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 × 4 bits Data FA00H memory space...
Page 49: Memory Map ( Μ Pd789445, 789455)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Memory Map ( PD789445, 789455) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 × 4 bits Data FA00H memory space...
Page 50: Memory Map ( Μ Pd789446, 789456)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Memory Map ( PD789446, 789456) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 × 4 bits Data FA00H memory space...
Page 51: Pd78F9456)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-6. Memory Map ( PD78F9456) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 × 4 bits Data FA00H memory space...
Page 52: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). µ PD789426, 789436, 789446, and 789456 Subseries provide internal ROM (or flash memory) with the following capacity for each product.
Page 53: Internal Data Memory (Internal High-Speed Ram) Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space µ PD789426, 789436, 789446, and 789456 Subseries products incorporate the following RAM. Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FD00H and FEFFH. The internal high-speed RAM is also used as a stack. LCD display RAM LCD display RAM is incorporated.
Page 54: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing µ PD789426, 789436, 789446, and 789456 Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area (FD00H to FFFFH) especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available.
Page 55: Data Memory Addressing ( Μ Pd789426, 789436)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-8. Data Memory Addressing ( PD789426, 789436) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH FD00H Register indirect...
Page 56: Pd78F9436)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-9. Data Memory Addressing ( PD78F9436) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH FD00H Register indirect...
Page 57: Data Memory Addressing ( Μ Pd789445, 789455)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-10. Data Memory Addressing ( PD789445, 789455) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH FD00H Register indirect...
Page 58: Data Memory Addressing ( Μ Pd789446, 789456)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-11. Data Memory Addressing ( PD789446, 789456) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH FD00H Register indirect...
Page 59: Pd78F9456)
CHAPTER 3 CPU ARCHITECTURE µ Figure 3-12. Data Memory Addressing ( PD78F9456) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH FD00H Register indirect...
Page 60: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers µ PD789426, 789436, 789446, and 789456 Subseries provide the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 61 CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable interrupt are all disabled. When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources.
Page 62: Stack Pointer Configuration
CHAPTER 3 CPU ARCHITECTURE Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-15. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10...
Page 63: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 64: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions.
Page 65 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Register List (1/2) Address Special Function Register (SFR) Name Symbol Bit Manipulation Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port 0 √ √ − FF01H Port 1 √...
Page 66 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Register List (2/2) Address Special Function Register (SFR) Name Symbol Bit Manipulation Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF27H Port mode register 7 √ √ − Note FF28H Port mode register 8...
Page 67: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 68: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 69: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 70: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 71: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 72: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 73: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 74: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.
Page 75: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
Page 76: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions µ PD789426, 789436, 789446, and 789456 Subseries provide the ports shown in Figures 4-1 and 4-2, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Page 77: Port Functions
CHAPTER 4 PORT FUNCTIONS µ Figure 4-2. Port Types ( PD789446, 789456 Subseries) Port 5 Port 0 Port 1 Port 6 Port 2 Port 7 Port 3 User’s Manual U15075EJ2V1UD...
Page 78 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (1/2) Pin Name Function After Reset Alternate Function P00 to P03 Port 0. Input KR0 to KR3 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00).
Page 79: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (2/2) Pin Name Function After Reset Alternate Function − Note P80, P81 Port 8. Input 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by setting pull-up resistor option register B8 (PUB8).
Page 80: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 This is a 4-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using the port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by setting pull-up resistor option register 0 (PU0).
Page 81: Block Diagram Of P10 And P11
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by setting pull-up resistor option register 0 (PU0).
Page 82: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register B2 (PUB2).
Page 83: Port 2
CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P21 and P26 PUB2 PUB21, PUB26 P-ch PORT Output latch P21/BZO90, (P21, P26) P26/TO90 PM21, PM26 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ2V1UD...
Page 84: Block Diagram Of P22
CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P22 PUB2 PUB22 P-ch Alternate function PORT Output latch P22/SS20 (P22) PM22 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ2V1UD...
Page 85: Block Diagram Of P23
CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P23 PUB2 PUB23 P-ch Alternate function PORT Output latch P23/ASCK20/ (P23) SCK20 PM23 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ2V1UD...
Page 86: Block Diagram Of P24
CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P24 PUB2 PUB24 P-ch PORT Output latch P24/SO20/TxD20 (P24) PM24 Alternate function SS20 output PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ2V1UD...
Page 87: Block Diagram Of P25
CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P25 PUB2 PUB25 P-ch Alternate function PORT Output latch P25/SI20/ (P25) RxD20 PM25 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ2V1UD...
Page 88: Block Diagram Of P30
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 4-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (PM3). When using the P30 to P33 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register B3 (PUB3).
Page 89: Port 3
CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 to P33 PUB3 PUB31 to PUB33 P-ch Alternate function PORT Output latch P31/INTP1/TO50/ (P31 to P33) TMI60, P32/INTP2/TO60, P33/INTP3/TO61 PM31 to PM33 Alternate function PUB3: Pull-up resistor option register B3 Port mode register Port 3 read signal Port 3 write signal...
Page 90: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option.
Page 91: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 This is a 6-bit input-only port. This port is also used as the analog input of an A/D converter. Figure 4-14 shows a block diagram of Port 6. Figure 4-14. Block Diagram of Port 6 P60/ANI0 to P65/ANI5 A/D converter −...
Page 92: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 This is a 3-bit I/O port with an output latch. Port 7 can be specified in the input or output mode in 1-bit units by using port mode register 7 (PM7). When using the P70 to P72 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register B7 (PUB7).
Page 93: Pd789426, 789436 Subseries Only)
CHAPTER 4 PORT FUNCTIONS µ 4.2.8 Port 8 ( PD789426, 789436 Subseries only) This is a 2-bit I/O port with an output latch. Port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (PM8). When using pins P80 and P81 as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register B8 (PUB8).
Page 94: Port 9 ( Μ Pd789426, 789436 Subseries Only)
CHAPTER 4 PORT FUNCTIONS µ 4.2.9 Port 9 ( PD789426, 789436 Subseries only) This is an 8-bit I/O port with an output latch. Port 9 can be specified in the input or output mode in 1-bit units by using port mode register 9 (PM9). When using the pins of this port as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register B9 (PUB9).
Page 95: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The ports are controlled by the following two types of registers. • Port mode registers (PM0 to PM3, PM5, PM7 to PM9) • Pull-up resistor option registers (PU0, PUB2, PUB3, PUB7 to PUB9) Port mode registers (PM0 to PM3, PM5, PM7 to PM9) These registers are used to set port input/output in 1-bit units.
Page 96: Format Of Port Mode Register
CHAPTER 4 PORT FUNCTIONS Figure 4-18. Format of Port Mode Register Symbol Address After reset PM03 PM02 PM01 PM00 FF20H PM13 PM12 PM11 PM10 FF21H PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM33 PM32 PM31 PM30 FF23H PM53 PM52 PM51 PM50 FF25H...
Page 97 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Alternate Function Pin Name PMxx Name P00 to P03 KR0 to KR3 Input TO90 Output INTP0 Input CPT90 Input INTP1 Input TO50 Output TMI60 Input INTP2...
Page 98 CHAPTER 4 PORT FUNCTIONS Pull-up resistor option register B2 (PUB2) Pull-up resistor option register B2 (PUB2) sets whether on-chip pull-up resistors on P20 to P26 are used or not. On the port specified to use an on-chip pull-up resistor by PUB2, the pull-up resistor can be internally used only for the bits set in the input mode.
Page 99 CHAPTER 4 PORT FUNCTIONS Pull-up resistor option register B7 (PUB7) Pull-up resistor option register B7 (PUB7) sets whether on-chip pull-up resistors on P70 to P72 are used or not. On the port specified to use an on-chip pull-up resistor by PUB7, the pull-up resistor can be internally used only for bits set in the input mode.
Page 100 CHAPTER 4 PORT FUNCTIONS Note Pull-up resistor option register B9 (PUB9) Pull-up resistor option register B9 (PUB9) sets whether on-chip pull-up resistors on P90 to P97 are used or not. On the port specified to use an on-chip pull-up resistor by PUB9, the pull-up resistor can be internally used only for bits set in the input mode.
Page 101: Port Function Operation
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 102: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. A main system clock oscillator and a subsystem clock oscillator are available as the system clock oscillator. Moreover, crystal/ceramic oscillation or RC oscillation can be selected for the main system clock oscillator by a mask option.
Page 103 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus FRC SCC Suboscillation mode register (SCKM) 16-bit timer 90 Subsystem 8-bit timer 60 clock Watch timer oscillator LCD controller/driver Prescaler Clock to peripheral hardware X1 or CL1 Main system clock Prescaler...
Page 104: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following registers. • Processor clock control register (PCC) • Suboscillation mode register (SCKM) • Subclock control register (CSS) User’s Manual U15075EJ2V1UD...
Page 105 CHAPTER 5 CLOCK GENERATOR Processor clock control register (PCC) PCC sets CPU clock selection and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 5-2. Format of Processor Clock Control Register Symbol <7>...
Page 106 CHAPTER 5 CLOCK GENERATOR Suboscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-3.
Page 107 CHAPTER 5 CLOCK GENERATOR Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the CPU clock operation status. CSS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSS to 00H.
Page 108: System Clock Oscillators
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators There are two types of system clock oscillators: the main system clock oscillator and the subsystem clock oscillator. The main system clock can be switched between crystal/ceramic oscillation and RC oscillation (mask option).
Page 109: Main System Clock Oscillator (Rc Oscillation) (Mask Option)
CHAPTER 5 CLOCK GENERATOR 5.4.2 Main system clock oscillator (RC oscillation) (mask option) This oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across the CL1 and CL2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and leave the CL2 pin open.
Page 110: Example Of Incorrect Resonator Connection
CHAPTER 5 CLOCK GENERATOR 5.4.4 Example of incorrect resonator connection Figure 5-8 shows an example of incorrect connection for crystal/ceramic oscillation and Figure 5-9 shows an example for RC oscillation. Figure 5-8. Examples of Incorrect Connection for Crystal/Ceramic Oscillation (1/2) (a) Too long wiring (b) Crossed signal line PORTn...
Page 111 CHAPTER 5 CLOCK GENERATOR Figure 5-8. Examples of Incorrect Connection for Crystal/Ceramic Oscillation (2/2) (e) Signal is fetched Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. User’s Manual U15075EJ2V1UD...
Page 112 CHAPTER 5 CLOCK GENERATOR Figure 5-9. Examples of Incorrect Connection for RC Oscillation (1/3) (a) Too long wiring • Main system clock • Subsystem clock (b) Crossed signal line • Main system clock • Subsystem clock PORTn (n = 0 to 3, 5 to 9) PORTn (n = 0 to 3, 5 to 9) User’s Manual U15075EJ2V1UD...
Page 113 CHAPTER 5 CLOCK GENERATOR Figure 5-9. Examples of Incorrect Connection for RC Oscillation (2/3) (c) Wiring near high fluctuating current • Main system clock • Subsystem clock High current High current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) •...
Page 114: Divider Circuit
CHAPTER 5 CLOCK GENERATOR Figure 5-9. Examples of Incorrect Connection for RC Oscillation (3/3) (e) Signal is fetched • Main system clock • Subsystem clock 5.4.5 Divider circuit The divider circuit divides the output of the main system clock oscillator (f ) to generate various clocks.
Page 115: Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock or f • Subsystem clock • CPU clock •...
Page 116: Changing Setting Of System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 117: Switching Between System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching between system clock and CPU clock When crystal/ceramic oscillation is selected The following describes switching between the system clock and CPU clock when crystal/ceramic oscillation is selected for the main system clock. Figure 5-10. Switching Between System Clock and CPU Clock (Crystal/Ceramic Oscillation) RESET Interrupt request signal System clock...
Page 118 CHAPTER 5 CLOCK GENERATOR When RC oscillation is selected The following describes switching between the system clock and CPU clock when RC oscillation is selected for the main system clock. Figure 5-11. Switching Between System Clock and CPU Clock (RC Oscillation) RESET Interrupt request signal System clock...
Page 119: Chapter 6 16-Bit Timer 90
CHAPTER 6 16-BIT TIMER 90 6.1 16-Bit Timer 90 Functions 16-bit timer 90 has the following functions. • Timer interrupt • Timer output • Buzzer output • Count value capture Timer interrupt An interrupt is generated when a count value and compare value matches. Timer output Timer output can be controlled when a count value and compare value matches.
Page 120: 16-Bit Timer 90 Configuration
CHAPTER 6 16-BIT TIMER 90 6.2 16-Bit Timer 90 Configuration 16-bit timer 90 includes the following hardware. Table 6-1. 16-Bit Timer 90 Configuration Item Configuration 16 bits × 1 (TM90) Timer counters 16 bits × 1 (CR90) Compare register: Registers 16 bits ×...
Page 121 Figure 6-1. Block Diagram of 16-Bit Timer 90 Internal bus 16-bit timer mode control register 90 (TMC90) TOF90 CPT901 CPT900 TOC90 TCL901TCL900 TOE90 PM26 Output latch TO90/P26 16-bit compare register TOD90 90 (CR90) Match INTTM90 Synchronization circuit BZO90/P21 16-bit timer counter 90 (TM90) CPT90/INTP0 /P30...
Page 122 CHAPTER 6 16-BIT TIMER 90 16-bit compare register 90 (CR90) A value specified in CR90 is compared with the count in 16-bit timer counter 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90. CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can be set.
Page 123: Registers Controlling 16-Bit Timer 90
CHAPTER 6 16-BIT TIMER 90 6.3 Registers Controlling 16-Bit Timer 90 16-bit timer 90 is controlled by the following four registers. • 16-bit timer mode control register 90 (TMC90) • Buzzer output control register 90 (BZC90) • Port mode registers 2, 3 (PM2, PM3) •...
Page 124 CHAPTER 6 16-BIT TIMER 90 Figure 6-2. Format of 16-Bit Timer Mode Control Register 90 Symbol <7> <6> <0> Address After reset Note TMC90 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 FF48H TOD90 Timer output data Timer output data is "0" Timer output data is "1"...
Page 125 CHAPTER 6 16-BIT TIMER 90 Buzzer output control register 90 (BZC90) This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and TCL900), and controls the output of the square wave. BZC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets BZC90 to 00H.
Page 126 CHAPTER 6 16-BIT TIMER 90 Port mode registers 2, 3 (PM2, PM3) PM2 and PM3 are used to set each bit of ports 2 and 3 to input or output. When the P26/TO90 pin is used for timer output, reset the output latch of P26 and PM26 to 0; when pin P21/BZO90 is used for buzzer output, reset the output latch of P26 and PM26 to 0.
Page 127: 16-Bit Timer 90 Operation
CHAPTER 6 16-BIT TIMER 90 6.4 16-Bit Timer 90 Operation 6.4.1 Operation as timer interrupt 16-bit timer 90 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR90. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is equal to one cycle of the count clock set in TCL901 and TCL900.
Page 128 CHAPTER 6 16-BIT TIMER 90 Figure 6-6. Timing of Timer Interrupt Operation Count clock TM90 count value 0000H 0001H 0000H 0001H FFFFH CR90 INTTM90 Interrupt Interrupt acknowledgment acknowledgment TO90 TOF90 Overflow flag set Remark N = 0000H to FFFFH User’s Manual U15075EJ2V1UD...
Page 129: Operation As Timer Output
CHAPTER 6 16-BIT TIMER 90 6.4.2 Operation as timer output 16-bit timer 90 can invert the timer output repeatedly each time the free-running counter value reaches the value set to CR90. Since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in TCL901 and TCL900.
Page 130: Capture Operation
CHAPTER 6 16-BIT TIMER 90 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer register 90 (TM90) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC90 as shown in Figure 6-9 to allow 16-bit timer 90 to start the capture operation. Figure 6-9.
Page 131: 16-Bit Timer Counter 90 Readout
CHAPTER 6 16-BIT TIMER 90 6.4.4 16-bit timer counter 90 readout The count value of 16-bit timer counter 90 (TM90) is read out using a 16-bit manipulation instruction. TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count value, and the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM90 lower byte rises, and the count value is retained.
Page 132: Buzzer Output Operation
CHAPTER 6 16-BIT TIMER 90 6.4.5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output. Table 6-4 shows the buzzer frequency.
Page 133: Notes On 16-Bit Timer 90
CHAPTER 6 16-BIT TIMER 90 6.5 Notes on 16-Bit Timer 90 6.5.1 Notes on using 16-bit timer 90 Usable functions differ according to the settings of the count clock selection, CPU clock operation, system clock oscillation status, and BZOE90 (bit 0 of buzzer output control register 90 (BZC90)). Refer to the following table.
Page 134 CHAPTER 6 16-BIT TIMER 90 Make the following settings when stopping the main system clock oscillation to support low current consumption and releasing the HALT mode. Count clock: Subsystem clock CPU clock: Subsystem clock Main system clock: Oscillation stopped BZOE90: 1 (Buzzer output enabled) At this time, when the setting of P21, the buzzer output alternate function pin, is “PM21 = 0, P21 = 0”, a square wave of the buzzer frequency is output from P21.
Page 135: Restrictions On Rewriting 16-Bit Compare Register 90
CHAPTER 6 16-BIT TIMER 90 6.5.2 Restrictions on rewriting 16-bit compare register 90 (1) When rewriting the compare register (CR90), be sure to disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) first. If CR90 is rewritten with interrupts enabled, an interrupt request may be generated at the point of rewrite. (2) The interval time may be double the intended time depending on the timing at which the compare register (CR90) is rewritten.
Page 136 CHAPTER 6 16-BIT TIMER 90 <Prevention method B> Rewriting by 16-bit access <1> Disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) <2> Rewrite CR90 (16 bits) <3> Wait for more than one cycle of the count clock <4>...
Page 137: Chapter 7 8-Bit Timers 50, 60
CHAPTER 7 8-BIT TIMERS 50, 60 7.1 8-Bit Timers 50, 60 Functions An 8-bit timer (one channel, timer 50) and an 8-bit timer/event counter (one channel, timer 60) are incorporated in µ PD789426, 789436, 799446, 789456 Subseries. The operation modes listed in the following table can be set via mode register settings.
Page 138: 8-Bit Timers 50, 60 Configuration
CHAPTER 7 8-BIT TIMERS 50, 60 Timer 60: Pulse generator mode The timer output status inverts repeatedly due to the settings of TM60, CR60, and CRH60, and pulses of any duty ratio are output (either P32/INTP2/TO60 or P33/INTP3/TO61 can be selected as the timer output pin using software).
Page 139 Figure 7-1. Block Diagram of Timer 50 Internal bus 8-bit timer mode control register 50 (TMC50) TEG50 TCE50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 PM31 output latch Decoder 8-bit compare register 50 (CR50) To Figure 7-2 (F) Match Timer 50 match signal (in cascade connection mode) Bit 7 of TM60 (from Figure 7-2 (A))
Page 140 Figure 7-2. Block Diagram of Timer 60 Internal bus Carrier generator output 8-bit timer mode control control register 60 (TCA60) register 60 (TMC60) 8-bit compare 8-bit compare TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE60 register 60 (CR60) RMC60 NRZB60 NRZ60 register H60 (CRH60) Decoder From Figure 7-1 (G)
Page 141 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-3. Block Diagram of Output Controller (Timer 60) TOE60 TOE61 PM32 PM33 Output latch Output latch TO60/P32/ INTP2 TO61/P33/ INTP3 Timer 60 output signal (1) 8-bit compare register 50 (CR50) This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer counter 50 (TM50) and to generate an interrupt request (INTTM50) when a match occurs.
Page 142 CHAPTER 7 8-BIT TIMERS 50, 60 (4) 8-bit timer counters 50 and 60 (TM50 and TM60) These are 8-bit registers that are used to count the count pulse. TM50 and TM60 are read with an 8-bit memory manipulation instruction. RESET input sets TM50 and TM60 to 00H. TM50 and TM60 are cleared to 00H under the following conditions.
Page 143 CHAPTER 7 8-BIT TIMERS 50, 60 (d) PWM output mode (i) TM50 • After reset • When the TCE50 flag is cleared to 0 • When a match occurs between TM50 and CR50 • When the TM50 count value overflows (ii) TM60 •...
Page 144: Registers Controlling 8-Bit Timers 50, 60
CHAPTER 7 8-BIT TIMERS 50, 60 7.3 Registers Controlling 8-Bit Timers 50, 60 8-bit timers 50 and 60 are controlled by the following five registers. • 8-bit timer mode control register 50 (TMC50) • 8-bit timer mode control register 60 (TMC60) •...
Page 145 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-4. Format of 8-Bit Timer Mode Control Register 50 Symbol <7> <6> <0> Address After reset TMC50 TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 FF4DH Note 1 TCE50 Control of TM50 count operation Clears TM50 count value and stops operation Starts count operation TEG50...
Page 146 CHAPTER 7 8-BIT TIMERS 50, 60 Notes 1. Since the count operation is controlled by TCE60 (bit 7 of TMC60) in cascade connection mode, any setting for TCE50 is ignored. The selection of both edges is valid only in the PWM output mode. In 8-bit counter mode or cascade connection mode, counting is done using the rising edge even if TEG50 is set to “1”.
Page 147 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-5. Format of 8-Bit Timer Mode Control Register 60 Symbol <7> <6> <0> Address After reset TMC60 TCE60 TOE61 TCL602 TCL601 TCL600 TMD601 TMD600 TOE60 FF4EH Note 1 TCE60 Control of TM60 count operation Clears TM60 count value and stops operation (the count value is also cleared for TM50 in cascade connection mode) Starts count operation (the count operation is also started for TM50 in cascade connection mode)
Page 148 CHAPTER 7 8-BIT TIMERS 50, 60 Caution When operating the TMC60, be sure to perform settings in the following order. <1> Stop the TM60 count operation. <2> Set the operation mode and the count clock. <3> Start count operation. Remarks 1. f : Main system clock oscillation frequency 2.
Page 149 CHAPTER 7 8-BIT TIMERS 50, 60 Cautions 1. Bits 3 to 7 must be set to 0. 2. TCA60 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8- bit memory manipulation instruction to set TCA60. 3.
Page 150: 8-Bit Timers 50, 60 Operation
CHAPTER 7 8-BIT TIMERS 50, 60 7.4 8-Bit Timers 50, 60 Operation 7.4.1 Operation as 8-bit timer counter Timer 50 and timer 60 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter. •...
Page 151 CHAPTER 7 8-BIT TIMERS 50, 60 Table 7-3. Interval Time of Timer 50 TCL502 TCL501 TCL500 Minimum Interval Time Maximum Interval Time Resolution µ µ µ (0.2 (51.2 (0.2 µ µ µ (1.6 (409.6 (1.6 µ µ (25.6 (25.6 (6.55 ms) µ...
Page 152 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start Count stop INTTMn0 Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement TOnm Interval time Interval time Interval time Remarks 1.
Page 153 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start INTTMn0 TOnm Remark n = 5, 6 nm = 50, 60, 61 Figure 7-11.
Page 154 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) Count clock N − 1 TMn0 Clear Clear Clear CRn0 TCEn0 TMn0 overflows because M < N INTTMn0 TOnm CRn0 overwritten...
Page 155 CHAPTER 7 8-BIT TIMERS 50, 60 Operation as external event counter with 8-bit resolution (timer 60 only) The external event counter counts the number of external clock pulses input to the TMI60/P31/INTP1/TO50 pin by using 8-bit timer counter 60 (TM60). To operate timer 60 as an external event counter, settings must be made in the following sequence.
Page 156 CHAPTER 7 8-BIT TIMERS 50, 60 Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register n0 (CRn0). To operate timer n0 for square-wave output, settings must be made in the following sequence. <1>...
Page 157 CHAPTER 7 8-BIT TIMERS 50, 60 Table 7-6. Square-Wave Output Range of Timer 60 (During f = 5.0 MHz Operation) TCL6 TCL601 TCL600 Minimum Pulse Width Maximum Pulse Width Resolution µ µ µ (0.2 (0.2 (51.2 µ µ (0.8 (2.04 ms) (0.8 input cycle ×...
Page 158: Operation As 16-Bit Timer Counter
CHAPTER 7 8-BIT TIMERS 50, 60 7.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits. 8-bit timer 60 controls reset and clear.
Page 159 CHAPTER 7 8-BIT TIMERS 50, 60 Table 7-7. Interval Time with 16-Bit Resolution (During f = 5.0 MHz Operation) TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time Resolution µ µ (0.2 (0.2 (13.1 ms) µ µ (0.8 (52.4 ms) (0.8 input cycle ×...
Page 160 Figure 7-16. Timing of Interval Timer Operation with 16-Bit Resolution Count clock TM60 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously CR60 TCE60 Count start TM50 count pulse...
Page 161 CHAPTER 7 8-BIT TIMERS 50, 60 Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI60/P31/INTP1/TO50 pin by TM50 and TM60. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence.
Page 162 Figure 7-17. Timing of External Event Counter Operation with 16-Bit Resolution TMI60 pin input TM60 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously CR60 TCE60 Count start...
Page 163 CHAPTER 7 8-BIT TIMERS 50, 60 Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 164 Figure 7-18. Timing of Square-Wave Output with 16-Bit Resolution Count clock TM60 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously CR60 TCE60 Count start TM50 count pulse X −...
Page 165: Operation As Carrier Generator
CHAPTER 7 8-BIT TIMERS 50, 60 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1>...
Page 166 CHAPTER 7 8-BIT TIMERS 50, 60 Cautions 1. TCA60 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8- bit memory manipulation instruction. 2. The NRZ60 flag can be rewritten only when the carrier generator output is stopped (TOE60 = 0).
Page 167 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-19. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) Count clock TM60 count value Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse TM50 CR50...
Page 168 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-20. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N) Count clock TM60 count value Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse TM50 CR50...
Page 169 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-21. Timing of Carrier Generator Operation (When CR60 = CRH60 = N) Count clock TM60 count value Clear Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse TM50 CR50 TCE50 INTTM50...
Page 170: Pwm Free-Running Mode Operation (Timer 50)
CHAPTER 7 8-BIT TIMERS 50, 60 7.4.4 PWM free-running mode operation (timer 50) In the PWM free-running mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio. To operate timer 50 in the PWM free-running mode, setting must be made in the following sequence.
Page 171 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-22. Operation Timing in PWM Free-Running Mode (When Rising Edge Is Selected) Count clock TM50 Overflow Overflow CR50 TCE50 Count start INTTM50 TO50 Caution When the rising edge is selected, do not set the CR50 to 00H. If the CR50 is set to 00H, PWM output may not be performed normally.
Page 172 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-23. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) (2/2) When setting CR50 < TM50 after overflow Count clock TM50 Overflow Overflow Overflow CR50 TCE50 Count start INTTM50 TO50 Overflow occurs but CR50 overwrite no change takes place because TO50 is...
Page 173 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-24. Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) (2/2) When CR50 = Odd number Count clock 2N + 1 TM50 2N + 1 Overflow Overflow Overflow CR50 2N + 1 TCE50 Count start INTTM50...
Page 174: Operation As Pwm Output (Timer 60)
CHAPTER 7 8-BIT TIMERS 50, 60 7.4.5 Operation as PWM output (timer 60) In the PWM pulse generator mode, a pulse of any duty ratio can be output by setting a low-level width using CR60 and a high-level width using CRH60. To operate timer 60 in PWM output mode, settings must be made in the following sequence.
Page 175 CHAPTER 7 8-BIT TIMERS 50, 60 Figure 7-26. PWM Pulse Generator Mode Timing (Basic Operation) Count clock TM60 count value Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 TO60 or Note TO61 Note The initial value of TO60 is low level when output is enabled (TOE60 = 1). Figure 7-27.
Page 176: Notes On Using 8-Bit Timers 50, 60
CHAPTER 7 8-BIT TIMERS 50, 60 7.5 Notes on Using 8-Bit Timers 50, 60 Error on starting timer An error of up to 1 clock is included in the time between the timer being started and a match signal being generated.
Page 177: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 is a block diagram of the watch timer. Figure 8-1.
Page 178: Watch Timer Configuration
CHAPTER 8 WATCH TIMER Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5- second interval.
Page 179: Watch Timer Control Register
CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer is controlled by the watch timer mode control register (WTM). • Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled.
Page 180: Watch Timer Operation
CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. The watch timer is used to generate an interrupt request at specified intervals. By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting.
Page 181 CHAPTER 8 WATCH TIMER Figure 8-3. Watch Timer/Interval Timer Operation Timing 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Interval timer (T) Caution When operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (WTM0) of the watch mode timer mode control register (WTM) to 1, the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the watch...
Page 182: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect a program runaway.
Page 183: Watchdog Timer Configuration
CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Figure 9-1. Block Diagram of Watchdog Timer Internal bus WDTMK Prescaler...
Page 184: Watchdog Timer Control Registers
CHAPTER 9 WATCHDOG TIMER 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock. WDCS is set with an 8-bit memory manipulation instruction.
Page 185 CHAPTER 9 WATCHDOG TIMER Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3.
Page 186: Watchdog Timer Operation
CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects a program runaway when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of watchdog timer clock select register (WDCS).
Page 187: Operation As Interval Timer
CHAPTER 9 WATCHDOG TIMER 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value.
Page 188: Chapter 10 8-Bit A/D Converter ( Μ Pd789426 And 789446 Subseries)
µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) 10.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter used to convert analog inputs into digital signals. This converter can control six channels (ANI0 to ANI5) of analog inputs. A/D conversion can only be started by software.
Page 189 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Figure 10-1. Block Diagram of 8-Bit A/D Converter P-ch ANI0/P60 ANI1/P61 Sample & hold circuit ANI2/P62 ANI3/P63 Voltage comparator ANI4/P64 ANI5/P65 Successive approximation register (SAR) Controller INTAD0 A/D conversion result register 0 (ADCR0) ADS02 ADS01 ADS00 ADCS0 FR02...
Page 190 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. Series resistor string The series resistor string is configured between AV and AV .
Page 191: 8-Bit A/D Converter Control Registers
µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) 10.3 8-Bit A/D Converter Control Registers The 8-bit A/D converter is controlled by the following two registers. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 192 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H.
Page 193: 8-Bit A/D Converter Operation
µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) 10.4 8-Bit A/D Converter Operation 10.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3>...
Page 194: Input Voltage And Conversion Result
µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Figure 10-4. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled.
Page 195 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result A/D conversion result (ADCR0) Input voltage/AV User’s Manual U15075EJ2V1UD...
Page 196: Operation Mode Of 8-Bit A/D Converter
µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) 10.4.3 Operation mode of 8-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI5 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).
Page 197: Cautions Related To 8-Bit A/D Converter
µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) 10.5 Cautions Related to 8-Bit A/D Converter Current consumption in standby mode In standby mode, the A/D converter stops operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 10-7 shows how to reduce the current consumption in standby mode.
Page 198 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress.
Page 199 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Noise prevention To maintain a resolution of 8 bits, watch for noise to the AV and ANI0 to ANI5 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 10-10.
Page 200 µ CHAPTER 10 8-BIT A/D CONVERTER ( PD789426 AND 789446 SUBSERIES) Figure 10-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion ADIF0 has been set, but conversion (to begin conversion for ANIn) for ANIm has not been completed.
Page 201: Chapter 11 10-Bit A/D Converter ( Pd789436 And 789456 Subseries)
µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) 11.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This converter can control six channels (ANI0 to ANI5) of analog inputs. A/D conversion can only be started by software.
Page 202 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Figure 11-1. Block Diagram of 10-Bit A/D Converter P-ch ANI0/P60 ANI1/P61 Sample & hold circuit ANI2/P62 ANI3/P63 Voltage comparator ANI4/P64 ANI5/P65 Successive approximation register (SAR) Controller INTAD0 A/D conversion result register 0 (ADCR0) ADS02 ADS01 ADS00 ADCS0 FR02...
Page 203 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string.
Page 204: 10-Bit A/D Converter Control Registers
µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) 11.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is controlled by the following two registers. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 205 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H.
Page 206: 10-Bit A/D Converter Operation
µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) 11.4 10-Bit A/D Converter Operation 11.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3>...
Page 207: Input Voltage And Conversion Result
µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Figure 11-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled.
Page 208 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1023 1022 1021 A/D conversion result (ADCR0) 2043 1022 2045 1023 2047 2048 1024 2048 1024 2048 1024 2048 1024 2048...
Page 209: Operation Mode Of 10-Bit A/D Converter
µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) 11.4.3 Operation mode of 10-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI5 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).
Page 210: Cautions Related To 10-Bit A/D Converter
µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) 11.5 Cautions Related to 10-Bit A/D Converter Current consumption in standby mode In standby mode, the A/D converter stops operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 11-7 shows how to reduce the current consumption in standby mode.
Page 211 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress.
Page 212 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Noise prevention To maintain a resolution of 10 bits, watch for noise to the AV and ANI0 to ANI5 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 11-10.
Page 213 µ CHAPTER 11 10-BIT A/D CONVERTER ( PD789436 AND 789456 SUBSERIES) Figure 11-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion (to begin conversion ADIF0 has been set, but conversion for ANIn) for ANIm) for ANIm has not been completed.
Page 214: Chapter 12 Serial Interface 20
CHAPTER 12 SERIAL INTERFACE 20 12.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit.
Page 215 Figure 12-1. Block Diagram of Serial Interface 20 Internal bus Serial operation mode Asynchronous serial interface Asynchronous serial interface register 20 (CSIM20) status register 20 (ASIS20) mode register 20 (ASIM20) Reception buffer TXE20 RXE20 PS201 PS200 CL20 SL20 CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 PE20 FE20 OVE20 register 20 (RXB20) Switching of the first bit...
Page 216 CHAPTER 12 SERIAL INTERFACE 20 Transmission shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit- serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission.
Page 217: Serial Interface 20 Control Registers
CHAPTER 12 SERIAL INTERFACE 20 12.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following six registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) •...
Page 218 CHAPTER 12 SERIAL INTERFACE 20 Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Figure 12-4.
Page 219 CHAPTER 12 SERIAL INTERFACE 20 Table 12-2. Serial Interface 20 Operating Mode Settings Operation stop mode ASIM20 CSIM20 PM25 PM24 PM23 First Shift P25/SI20/ P24/SO20/ P23/SCK20/ Clock RxD20 Pin TxD20 Pin ASCK20 Pin TXE20 RXE20 CSIE20 DIR20 CSCK20 Function Function Function ×...
Page 220 CHAPTER 12 SERIAL INTERFACE 20 Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode.
Page 221 CHAPTER 12 SERIAL INTERFACE 20 Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Figure 12-6. Format of Baud Rate Generator Control Register 20 Symbol Address After reset...
Page 222 CHAPTER 12 SERIAL INTERFACE 20 The transmit/receive clock for the baud rate to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the ASCK20 pin. (a) Generation of UART transmit/receive clock for baud rate from system clock The transmit/receive clock is generated by scaling the system clock.
Page 223 CHAPTER 12 SERIAL INTERFACE 20 (b) Generation of UART transmit/receive clock for baud rate from external clock input from ASCK20 The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression.
Page 224: Serial Interface 20 Operation
CHAPTER 12 SERIAL INTERFACE 20 12.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 12.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. P23/SCK20/ASCK20, P24/SO20/TxD20, and P25/SI20/RxD20 pins can be used as normal I/O ports.
Page 225 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 226: Asynchronous Serial Interface (Uart) Mode
CHAPTER 12 SERIAL INTERFACE 20 12.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. This device incorporates UART-dedicated baud rate generator that enables communications at the desired baud rate.
Page 227 CHAPTER 12 SERIAL INTERFACE 20 (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM20 to 00H. Set CSIM20 to 00H when UART mode is selected. Symbol <7> Address After reset CSIM20...
Page 228 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 229 CHAPTER 12 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS20 to 00H. Symbol <2> <1> <0> Address After reset ASIS20 PE20 FE20 OVE20 FF71H PE20...
Page 230 CHAPTER 12 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol Address After reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator...
Page 231 CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the ASCK20 pin. (i) Generation of transmit/receive clock for baud rate from system clock The transmit/receive clock is generated by scaling the system clock.
Page 232 CHAPTER 12 SERIAL INTERFACE 20 (ii) Generation of transmit/receive clock for baud rate from external clock input from ASCK20 The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression.
Page 233 CHAPTER 12 SERIAL INTERFACE 20 Communication operation (a) Data format The transmit/receive data format is as shown in Figure 12-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20).
Page 234 CHAPTER 12 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 235 CHAPTER 12 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmission shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Page 236 CHAPTER 12 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by BRGC20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 237 CHAPTER 12 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20).
Page 238 CHAPTER 12 SERIAL INTERFACE 20 Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmission shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission.
Page 239: 3-Wire Serial I/O Mode
CHAPTER 12 SERIAL INTERFACE 20 12.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: a serial clock (SCK20), serial output (SO20), and serial input (SI20).
Page 240 CHAPTER 12 SERIAL INTERFACE 20 (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM20 to 00H. Symbol <7> Address After reset CSIM20 CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 FF72H CSIE20 3-wire serial I/O mode operation control...
Page 241 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol <7>...
Page 242 CHAPTER 12 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol Address After reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator...
Page 243 CHAPTER 12 SERIAL INTERFACE 20 Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmission shift register (TXS20/SIO20) and reception shift register (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20).
Page 244 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 SI20 SO20 Note INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20...
Page 245 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 SO20 SI20 INTCSI20 (v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 write SCK20...
Page 246 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 write SCK20 Note 1 SIO20 write (master) SI20 Hi-Z Hi-Z Note 2 SO20 INTCSI20 Notes 1.
Page 247 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 Note SIO20 write (master) SI20 SO20 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20.
Page 248 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 SO20 Note SI20 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 write...
Page 249 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 write SCK20 SI20 Hi-Z Hi-Z Note 2 Note 1 SO20 INTCSI20 Notes 1. The value of the last bit previously output is output. 2.
Page 250: Chapter 13 Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions µ The functions of the LCD controller/driver of the PD789426, 789436, 789446, and 789456 Subseries are as follows. Automatic output of segment and common signals based on automatic display data memory read Two different display modes: •...
Page 251 Figure 13-1. Block Diagram of LCD Controller/Driver Internal bus LCD clock control LCD display mode LCD voltage boost Display data memory register 0 (LCDC0) register 0 (LCDM0) control register 0 (LCDVA0) FA00H ..FA04H FA05H ..FA0EH LCDC03 LCDC02 LCDC01 LCDC00 LIPS0 LCDM00 LCDON0...
Page 252: Registers Controlling Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.3 Registers Controlling LCD Controller/Driver • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • LCD voltage amplification control register 0 (LCDVA0) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display operation. It also specifies the operation mode, LCD drive power supply, and display mode.
Page 253 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-2. Format of LCD Display Mode Register 0 Symbol <7> <6> <4> Address After reset LCDM0 LCDON0 VAON0 LIPS0 LCDM00 FFB0H LCDON0 LCD display enable/disable Display off Display on Note VAON0 LCD controller/driver operation mode No internal voltage amplification (Normal operation) Internal voltage amplification enabled (Low-voltage operation) Note...
Page 254 CHAPTER 13 LCD CONTROLLER/DRIVER LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and number of time slices. LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H.
Page 255 CHAPTER 13 LCD CONTROLLER/DRIVER LCD voltage amplification control register 0 (LCDVA0) LCDVA0 controls the voltage amplification level during the voltage amplifier operation. LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDVA0 to 00H. Figure 13-4. Format of LCD Voltage Amplification Control Register 0 Symbol <0>...
Page 256: Setting Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the frame frequency using LCD clock control register 0 (LCDC0). <2> Set the voltage amplification level using LCD voltage amplification control register 0 (LCDVA0). GAIN = 0: V = 4.5 V, V = 3 V, V...
Page 257: Common And Segment Signals
CHAPTER 13 LCD CONTROLLER/DRIVER 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes a specific voltage (LCD drive voltage, V ) or higher. It turns off when the potential difference becomes lower than V Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it.
Page 258 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-6 shows the common signal waveforms, and Figure 13-7 shows the voltages and phases of the common and segment signals. Figure 13-6. Common Signal Waveforms COMn (Three-time slot mode) = 3 × T COMn (Four-time slot mode) = 4 ×...
Page 259: Display Modes
CHAPTER 13 LCD CONTROLLER/DRIVER 13.7 Display Modes 13.7.1 Three-time slot display example Figure 13-9 shows how the 5-digit LCD panel having the display pattern shown in Figure 13-8 is connected to the µ µ segment signals (S0 to S14) and the common signals (COM0 to COM2) of the PD789446 or PD789456 Subseries chip.
Page 260 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-9. Example of Connecting Three-Time Slot LCD Panel Open COM 3 COM 2 COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 x’: Can be used to store any data because there is no corresponding segment in the LCD panel. ×: Can always be used to store any data because of the three-time slot mode being used.
Page 261 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-10. Three-Time Slot LCD Drive Waveform Examples COM0 COM1 COM2 +1/3V COM0-S6 −1/3V −V +1/3V COM1-S6 −1/3V −V +1/3V COM2-S6 −1/3V −V User’s Manual U15075EJ2V1UD...
Page 262: Four-Time Slot Display Example
CHAPTER 13 LCD CONTROLLER/DRIVER 13.7.2 Four-time slot display example Figure 13-12 shows how the 7-digit LCD panel having the display pattern shown in Figure 13-11 is connected to µ µ the segment signals (S0 to S14) and the common signals (COM0 to COM3) of the PD789446 or PD789456 Subseries chip.
Page 263 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-12. Example of Connecting Four-Time Slot LCD Panel COM 3 COM 2 COM 1 COM 0 FA00H User’s Manual U15075EJ2V1UD...
Page 264 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-13. Four-Time Slot LCD Drive Waveform Examples COM0 COM1 COM2 COM3 +1/3V COM0-S2 −1/3V −V +1/3V COM1-S2 −1/3V −V Remark The waveforms of COM2-S2 and COM3-S2 are omitted. User’s Manual U15075EJ2V1UD...
Page 265: Supplying Lcd Drive Voltages
CHAPTER 13 LCD CONTROLLER/DRIVER 13.8 Supplying LCD Drive Voltages V , and V µ PD789426, 789436, 789446, 789456 Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The internal LCD reference voltage is output from the V pin.
Page 266: Chapter 14 Interrupt Functions
CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 267 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Basic External Configuration Table Name Trigger Note 2 Type Address − Non-maskable INTWDT Watchdog timer overflow (with Internal 0004H watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow (with interval...
Page 268 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (C) External maskable interrupt Internal bus INTM0, INTM1, KRM00...
Page 269: Registers Controlling Interrupt Function
CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. • Interrupt request flag registers 0, 1 (IF0 and IF1) • Interrupt mask flag registers 0, 1 (MK0 and MK1) •...
Page 270 CHAPTER 14 INTERRUPT FUNCTIONS Interrupt request flag registers 0, 1 (IF0 and IF1) The interrupt request flag is set (1) when the corresponding interrupt request is generated or an instruction is executed. It is cleared (0) when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input.
Page 271 CHAPTER 14 INTERRUPT FUNCTIONS Interrupt mask flag registers 0, 1 (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 14-3.
Page 272 CHAPTER 14 INTERRUPT FUNCTIONS External interrupt mode register 0 (INTM0) This register is used to specify a valid edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Figure 14-4. Format of External Interrupt Mode Register 0 Address After reset Symbol...
Page 273 CHAPTER 14 INTERRUPT FUNCTIONS External interrupt mode register 1 (INTM1) INTM1 is used to specify a valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-5. Format of External Interrupt Mode Register 1 Symbol Address After reset...
Page 274 CHAPTER 14 INTERRUPT FUNCTIONS Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (falling edge of port 0). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM00 to 00H. Figure 14-7.
Page 275: Interrupt Servicing Operation
CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operation 14.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 276 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-9. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT:...
Page 277: Maskable Interrupt Request Acknowledgment Operation
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 278: Multiple Interrupt Servicing
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock Saving PSW and PC, and MOV A, r Interrupt servicing program jump to interrupt servicing Interrupt If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n −...
Page 279 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-15. Example of Multiple Interrupts Example 1. Acknowledging multiple interrupts Main servicing INTxx servicing INTyy servicing IE = 0 IE = 0 INTxx INTyy RETI RETI The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are performed.
Page 280: Putting Interrupt Requests On Hold
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows.
Page 281: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 282: Register Controlling Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 283: Standby Function Operation
CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 15-1. HALT Mode Operating Status Item HALT Mode Operation Status While The Main HALT Mode Operation Status While The...
Page 284 CHAPTER 15 STANDBY FUNCTION Releasing HALT mode The HALT mode can be released by the following three types of sources: Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed.
Page 285 CHAPTER 15 STANDBY FUNCTION Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 15-3. Releasing HALT Mode by RESET Input Wait HALT : 6.55 ms)
Page 286: Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 287 CHAPTER 15 STANDBY FUNCTION Releasing STOP mode The STOP mode can be released by the following two types of sources: Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed.
Page 288 CHAPTER 15 STANDBY FUNCTION Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 15-5. Releasing STOP Mode by RESET Input STOP Wait instruction RESET signal...
Page 289: Chapter 16 Reset Function
CHAPTER 16 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer runaway time detection External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 290 CHAPTER 16 RESET FUNCTION Figure 16-2. Reset Timing by RESET Input Oscillation During normal Reset period Normal operation stabilization operation (oscillation stops) (reset processing) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 16-3. Reset Timing by Overflow in Watchdog Timer Oscillation Reset period During normal...
Page 291 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 292 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (2/2) Hardware Status After Reset LCD controller/driver Display mode register (LCDM0) Clock control register (LCDC0) Voltage amplification control register (LCDVA0) Interrupt Request flag register (IF0, IF1) Mask flag register (MK0, MK1) External interrupt mode register (INTM0, INTM1) Key return mode register (KRM00) User’s Manual U15075EJ2V1UD...
Page 293: Chapter 17 Pd78F9436, 78F9456
µ CHAPTER 17 PD78F9436, 78F9456 µ µ PD78F9436 is a version with the internal ROM of the PD789426 and 789436 Subseries replaced with flash µ µ memory and the PD78F9456 is a version with the internal ROM of the PD789446 and 789456 Subseries replaced µ...
Page 294: Flash Memory Characteristics
µ CHAPTER 17 PD78F9436, 78F9456 17.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- µ PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the PD78F9436 or 78F9456 mounted on the target system (on-board).
Page 295: Communication Mode
µ CHAPTER 17 PD78F9436, 78F9456 17.1.2 Communication mode Use the communication mode shown in Table 17-2 to perform communication between the dedicated flash µ programmer and PD78F9436 or 78F9456. Table 17-2. Communication Mode List Note 1 Communication TYPE Setting Pins Used Number of V Mode Pulses...
Page 296 µ CHAPTER 17 PD78F9436, 78F9456 Figure 17-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O µ Dedicated flash programmer PD78F9436, 78F9456 VPP1 RESET RESET SCK20 SI20 SO20 Note 1 (b) UART µ Dedicated flash programmer PD78F9436, 78F9456 VPP1 RESET RESET...
Page 297 µ CHAPTER 17 PD78F9436, 78F9456 If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash µ programmer, the following signals are generated for the PD78F9436 and 78F9456. For details, refer to the manual of Flashpro III/Flashpro IV.
Page 298: On-Board Pin Connections
µ CHAPTER 17 PD78F9436, 78F9456 17.1.3 On-board pin connections When programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. There may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required.
Page 299 µ CHAPTER 17 PD78F9436, 78F9456 Signal conflict A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin (input) connected to another device (output). To prevent this signal conflict, isolate the connection with the other device or put the other device in the output high impedance status.
Page 300 µ CHAPTER 17 PD78F9436, 78F9456 <RESET pin> When the reset signal of the dedicated flash programmer is connected to the RESET signal connected to the reset signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the connection with the reset signal generator.
Page 301: Connection Of Adapter For Flash Writing
µ CHAPTER 17 PD78F9436, 78F9456 17.1.4 Connection of adapter for flash writing The following figures show examples of the recommended connection when the adapter for flash writing is used. Figure 17-8. Wiring Example for Flash Writing Adapter Using 3-Wire Serial I/O VDD (2.7 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 µ...
Page 302 µ CHAPTER 17 PD78F9436, 78F9456 Figure 17-9. Wiring Example for Flash Writing Adapter Using UART VDD (2.7 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 µ PD78F9436 µ PD78F9456 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD2 (LVDD) CLKOUT RESET VPP RESERVE/HS...
Page 303: Chapter 18 Mask Options
CHAPTER 18 MASK OPTIONS µ The mask ROM versions of the PD789426, 789436, 789446, and 789456 Subseries have the following mask options. • Pull-up resistor The connection of on-chip pull-up resistors for port 5 (I/O port) can be switched in 1-bit units. <1>...
Page 304: Chapter 19 Instruction Set
CHAPTER 19 INSTRUCTION SET µ This chapter lists the instruction set of the PD789426, 789436, 789446, and 789456 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in “Operand”...
Page 305: Description Of "Operation" Column
CHAPTER 19 INSTRUCTION SET 19.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 306: Operation List
CHAPTER 19 INSTRUCTION SET 19.2 Operation List Mnemonic Operands Byte Clock Operation Flag Z AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 307 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 308 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A, CY ← A − byte − CY SUBC A, #byte (saddr), CY ← (saddr) − byte − CY saddr, #byte A, CY ← A − r − CY A, r A, CY ←...
Page 309 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A − byte A, #byte (saddr) − byte saddr, #byte A − r A, r A − (saddr) A, saddr A − (addr16) A, !addr16 A − (HL) A, [HL] A −...
Page 310 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 311: Instructions Listed By Addressing Type
CHAPTER 19 INSTRUCTION SET 19.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] [HL+byte] $addr1 None 1st Operand Note...
Page 312 CHAPTER 19 INSTRUCTION SET 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand...
Page 313 CHAPTER 19 INSTRUCTION SET Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic Instructions CALL CALLT Compound Instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U15075EJ2V1UD...
Page 314 CHAPTER 20 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit Power supply voltage = AV –0.3 to +6.5 µ PD78F9436, 78F9456 only, Note 1 –0.3 to +10.5 Note 3 Input voltage P00 to P03, P10, P11, P20 to P26, P30 to –0.3 to V + 0.3 Note 2...
Page 315: Chapter 20 Electrical Specifications
CHAPTER 20 ELECTRICAL SPECIFICATIONS Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Page 316 CHAPTER 20 ELECTRICAL SPECIFICATIONS Main System Clock Oscillator Characteristics Ceramic/crystal oscillation = –40 to +85°C, V = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Note 1 Ceramic Oscillation frequency (f resonator Oscillation stabilization After V reaches Note 2 time...
Page 317 CHAPTER 20 ELECTRICAL SPECIFICATIONS RC oscillation (mask option) = –40 to +85°C, V = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit RC resonator Oscillation frequency = Oscillation Notes 1,2 voltage range µ Oscillation = 2.7 to 5.5 V Note 3 stabilization time µ...
Page 318 CHAPTER 20 ELECTRICAL SPECIFICATIONS Subsystem Clock Oscillator Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal Oscillation frequency 32.768 Note 1 resonator Oscillation stabilization = 4.5 to 5.5 V Note 2 time = 1.8 to 5.5 V...
Page 319 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, low Per pin All pins Output current, high Per pin –1 All pins –15 Input voltage, high P10, P11, P60 to P65, = 2.7 to 5.5 V...
Page 320 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ Input leakage current, P00 to P03, P10, P11, LIH1 high P20 to P26, P30 to P33, P60 to P65, P70 to P72, Note 1 Note 1...
Page 321 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Power supply 5.0 MHz crystal oscillation Note 1 current operation mode = 3.0 V ±10% Note 3 0.36...
Page 322 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Power supply 5.0 MHz crystal oscillation Note 1 current operation mode = 3.0 V ±10% Note 3 µ...
Page 323 CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ Cycle time (minimum Operating with main = 2.7 to 5.5 V instruction execution system clock µ...
Page 324 CHAPTER 20 ELECTRICAL SPECIFICATIONS (2) Serial interface 20 (T = –40 to +85°C, V = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time = 2.7 to 5.5 V KCY1 = 1.8 to 5.5 V 3200...
Page 325 CHAPTER 20 ELECTRICAL SPECIFICATIONS (d) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time = 2.7 to 5.5 V KCY3 = 1.8 to 5.5 V 3200 ASCK20 high-/low- = 2.7 to 5.5 V level width = 1.8 to 5.5 V 1600 Transfer rate...
Page 326 CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Timing Measurement Points (excluding X1 (CL1) and XT1 inputs) 0.8V 0.8V Point of measurement 0.2V 0.2V Clock Timing (MIN.) X1 (CL1) input (MAX.) (MIN.) XT1 input (MAX.) Capture Input Timing CPTL CPTH CPT90 TMI Timing TMI60 Interrupt Input Timing INTL...
Page 327 CHAPTER 20 ELECTRICAL SPECIFICATIONS RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK20 SIKm KSIm SI20 Input data KSOm Output data SO20 Remark m = 1, 2 3-wire serial I/O mode (when using SS20): SS20 KAS2 KDS2 SO20 Output data...
Page 328 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ 8-Bit A/D Converter Characteristics ( PD789425, 789426, 789445, 789446) = –40 to +85°C, 1.8 V ≤ AV ≤ 5.5 V, AV =0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution ±0.6 Note Overall error = 2.7 to 5.5 V %FSR ±1.2...
Page 329 CHAPTER 20 ELECTRICAL SPECIFICATIONS LCD Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ Note 1 C1 to C4 = 0.47 LCD output voltage GAIN = 1 0.84 1.165 LCD2 variation range GAIN = 0...
Page 330 CHAPTER 20 ELECTRICAL SPECIFICATIONS Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode DDDR SREL STOP instruction execution RESET WAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode STOP mode Operation mode...
Page 331 CHAPTER 20 ELECTRICAL SPECIFICATIONS Flash Memory Write/Erase Characteristics (T = 10 to 40°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Operating frequency = 2.7 to 5.5 V = 1.8 to 5.5 V 1.25 Note Write current When V supply...
Page 332: Chapter 21 Characteristics Curves Of Lcd Controller/Driver
CHAPTER 21 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES) (1) Characteristics curves of voltage amplification stabilization time The following shows the characteristics curves of the time from the start of voltage amplification (VAON0 = 1) and the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)). LCD output voltage/Voltage amplification time 4.5 V 5.5 V...
Page 333 CHAPTER 21 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES) (2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD output voltage/ Temperature (When GAIN = 1) LCD2 LCD1 LCD0 −40 −30 −20 −10 Temperature [˚C]...
Page 334: Chapter 22 Package Drawings
CHAPTER 22 PACKAGE DRAWINGS 64-PIN PLASTIC TQFP (12x12) detail of lead end ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.125 1.125 0.32 +0.06 −0.10 0.13 0.65 (T.P.) 1.0±0.2 NOTE 0.17 +0.03 −0.07 Each lead centerline is located within 0.13 mm of 0.10 its true position (T.P.) at maximum material condition.
Page 335 CHAPTER 22 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.) NOTE 1.0±0.2 Each lead centerline is located within 0.08 mm of 0.17 +0.03 its true position (T.P.) at maximum material condition. −0.07 0.08 0.1±0.05...
Page 336: Chapter 23 Recommended Soldering Conditions
µ PD789426, 789436, 789446, and 789456 Subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website.
Page 337 CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Table 23-1. Surface Mounting Type Soldering Conditions (2/3) µ PD789425GB-×××-8EU: 64-pin plastic LQFP (10 × 10) µ PD789426GB-×××-8EU: 64-pin plastic LQFP (10 × 10) µ PD789435GB-×××-8EU: 64-pin plastic LQFP (10 × 10) µ PD789436GB-×××-8EU: 64-pin plastic LQFP (10 × 10) µ...
Page 338 Wave soldering When the pin pitch of the package is 0.65 mm or more, wave soldering can also be performed. For details, contact an NEC Electronics sales representative. − Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) Caution Do not use different soldering methods together (except for partial heating).
Page 339: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS µ The following development tools are available for development of systems using the PD789426, 789436, 789446, and 789456 Subseries. Figure A-1 shows development tools. • Support to PC98-NX Series Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in PC98-NX Series.
Page 340 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package · Software package Language processing software Debugging software · Assembler package · Integrated debugger · C compiler package · System simulator · Device file · Note 1 C library source file Control software ·...
Page 341: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Various software tools for 78K/0S development are integrated in one package. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0-NS, SM78K0S, various device files µ Part number: S××××SP78K0S ×××× in the part number differs depending on the operating system used. Remark µ...
Page 342: Control Software
APPENDIX A DEVELOPMENT TOOLS ×××× in the part number differs depending on the host machine and operating system used. Remark µ S××××RA78K0S µ S××××CC78K0S ×××× Host Machine Supply Media AB13 PC-9800 series, Japanese Windows 3.5" 2HD FD IBM PC/AT and compatibles BB13 English Windows AB17...
Page 343: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using the In-circuit emulator 78K/0S Series. Can be used with an integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine.
Page 344: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the Integrated debugger 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 345: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following shows the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Among the products described in this appendix, NP-64GB-TQ, NP-H64GB-TQ, NP-64GK, and NP-H64GK-TQ are products of Naito Densei Machida Mfg.
Page 346 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When NP-64GB-TQ Is Used) Emulation board IE-789456-NS-EM1 Emulation probe NP-64GB-TQ 22 mm Conversion adapter TGB-064SDP 11 mm 16 mm 16 mm 40 mm 34 mm Target system Figure B-3.
Page 347 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-4. Distance Between In-Circuit Emulator and Conversion Adapter (When 64GK Is Used) In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789456-NS-EM1 Note 170 mm Emulation probe Conversion adapter NP-64GK, NP-H64GK-TQ TGK-064SBW Note Distance when NP-64GK is used.
Page 348 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-6. Connection Conditions of Target System (When NP-H64GK-TQ Is Used) Emulation board IE-789456-NS-EM1 Emulation probe NP-H64GK-TQ 21.95 mm Conversion adapter 11 mm TGK-064SBW 23 mm 18.4 mm 18.4 mm 42 mm 45 mm Target system User’s Manual U15075EJ2V1UD...
Page 349: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (Alphabetic Order of Register Name) Analog input channel specification register 0 (ADS0)................... 192, 205 A/D conversion result register 0 (ADCR0)....................189, 202 A/D converter mode register 0 (ADM0) ......................191, 204 Asynchronous serial interface mode register 20 (ASIM20) ............219, 226, 229, 242 Asynchronous serial interface status register 20 (ASIS20) ................
Page 350 APPENDIX C REGISTER INDEX Port 1 (P1) ................................81 Port 2 (P2) ................................82 Port 3 (P3) ................................88 Port 5 (P5) ................................90 Port 6 (P6) ................................91 Port 7 (P7) ................................92 Port 8 (P8) ................................93 Port 9 (P9) ................................94 Port mode register 0 (PM0)............................
Page 351 APPENDIX C REGISTER INDEX C.2 Register Index (Alphabetic Order of Register Symbol) ADCR0: A/D conversion result register 0 ....................189, 202 ADM0: A/D converter mode register 0..................... 191, 204 ADS0: Analog input channel specification register 0 ................192, 205 ASIM20: Asynchronous serial interface mode register 20............219, 226, 229, 242 ASIS20: Asynchronous serial interface status register 20 .................
Page 352 APPENDIX C REGISTER INDEX Port 5 ..............................90 Port 6 ..............................91 Port 7 ..............................92 Port 8 ..............................93 Port 9 ..............................94 PCC: Processor clock control register ......................105 PM0: Port mode register 0 ..........................95 PM1: Port mode register 1 ..........................95 PM2: Port mode register 2 ........................95, 126 PM3:...
Page 353: Appendix D Revision History
APPENDIX D REVISION HISTORY Revisions up to this edition are shown below. The “Applied to” column indicates the chapter in each edition to which the revision was applied. (1/2) Edition Description Applied to • Addition throughout of description of RC oscillation CHAPTER 1 GENERAL •...
Page 354 APPENDIX D REVISION HISTORY (2/2) Edition Description Applied to Addition of chapter CHAPTER 20 ELECTRICAL SPECIFICATIONS CHAPTER 21 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) CHAPTER 22 PACKAGE DRAWINGS CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Total revision of appendix APPENDIX A DEVELOPMENT TOOLS Addition of appendix APPENDIX B NOTES ON...

This manual is also suitable for:

U789436 series U789446 series U789456 series Upd789425 Upd789445Upd789426 ... Show all

NEC UPD789426 Series User Manual

Chapter 1 General

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer 90

Chapter 7 8-Bit Timers 50, 60

Chapter 8 Watch Timer

Chapter 9 Watchdog Timer

CHAPTER 10 8-BIT A/D CONVERTER ( Μ PD789426 and 789446 SUBSERIES)

Chapter 11 10-Bit A/D Converter ( Pd789436 and 789456 Subseries)

Chapter 12 Serial Interface 20

Chapter 13 Lcd Controller/Driver

Chapter 14 Interrupt Functions

Chapter 15 Standby Function

Chapter 16 Reset Function

Chapter 17 Pd78F9436, 78F9456

Chapter 18 Mask Options

Chapter 19 Instruction Set

Chapter 20 Electrical Specifications

Chapter 21 Characteristics Curves of Lcd Controller/Driver

Chapter 22 Package Drawings

Chapter 23 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Notes on Target System Design

Appendix C Register Index

Appendix D Revision History

Quick Links

Related Manuals for NEC UPD789426 Series

Summary of Contents for NEC UPD789426 Series