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8.3 CW Unit EZU-ST5,EZU-CW4
8.3.1 CW PCB
No.
Signal Name
1 T̲CWS<23..0>
2 STCW<23..0>
3 STCW‑N<23..0>
4 STCW‑P<23..0>
5 USRF‑I<15..0>
6 USRF‑Q<15..0>
7 CWADCLK̲N
8 CWADCLK̲P
9 CK4F0CW‑N
10 CK4F0CW‑P
11 DBF‑CW‑D
12 CW̲CK
13 CW̲LCK
14 CW‑DBF‑D
15 STCWEN‑N
16 STCWEN‑P
17 CWCONFDONE
18 SYSRESET*
19 FPGARESET*
Terminal No.
IN/OUT
5D〜5A,
4E〜4A,
3E〜3A,
2E〜2A,
1E〜1A
11D〜11A,
10E〜10A,
9E〜9A,
8E〜8A,
7E〜7A
29D〜29A,
26E〜26A,
23E〜23A,
19E〜19A,
16E〜16A
30D〜30A,
27E〜27A,
24E〜24A,
20E〜20A,
17E〜17A
111A,
110E〜110A,
109E〜109A,
108E〜108A
114B〜114A,
113E〜113A,
112E〜112A,
111E〜111B
114E
114D
104A
105A
94D
91D
94E
105C
102D
103D
103A
100B
100A
From/To
IN
DBF‑29D〜29A,
28E〜28A,
27E〜27A,
26E〜26A,
25E〜25A
OUT
AWP‑37B, 36E,
36C, 36A, 35D,
35B, 34E, 34C,
34A, 33D, 33B,
32E, 32C, 32A,
31D, 31B, 30E,
30C, 30A, 29D,
29B, 28E, 28C,
28A
IN
AWP‑80D〜80A,
77E〜77A,
74E〜74A,
71E〜71A,
68E〜68A
IN
AWP‑81D〜81A,
78E〜78A,
75E〜75A,
72E〜72A,
69E〜69A
OUT
EPI‑CNF1‑31, 29,
27, 25, 23, 21, 19,
17, 15, 13, 11, 9,
7, 5, 3, 1
OUT
EPI‑CNF1‑79, 77,
75, 73, 71, 69, 67,
65, 63, 61, 59, 57,
55, 53, 51, 49
IN
EPI‑CNF4‑37
IN
EPI‑CNF4‑39
IN
EPI‑CNF4‑5
IN
EPI‑CNF4‑7
IN
DBF‑109D
IN
DBF‑108D
IN
DBF‑107D
OUT
DBF‑110D
IN
DBF‑114D
IN
DBF‑113D
OUT
EPI‑CNF2‑29
IN
EPI‑CNF2‑75
IN
EPI‑CNF2‑73
8 - 16
Description
Steerable CW Transmission input
Signal
Steerable CW Transmission output
Signal
Steerable CW Reception Signal
Steerable CW Reception Signal
CW A/D Output Signal
CW A/D Output Signal
CW A/D clock.
CW A/D clock.
4 times reference clock for CWREC
(LVDS Negative pole).
4 times reference clock for CWREC
(LVDS Positive pole).
Control data (serial)
Clock for control data
Clock to set control data
CW version Data(serial)
Steering CW mode control.
Steering CW mode control.
FPGA config completion data
System Reset. Asserted at power on
and software boot.
FPGA reset.
FPGA configuration begins after
FPGARESET* positive edge.
L1E-EA0229
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