Hitachi EUB-5500 Technical Manual page 61

from DBF
24
USRF-I
P/S
(Fujinon Data)
24
Conv.
USRF-Q
125MHz
OSC.
System ID
to F/E,BIO,Fujinon
24 24
LPF Decim
Clock
Generator
US-Sync
Generator
sPCI-Bus (Local-Bus) sPCI-Bus sPCI-Bus sPCI-Bus (Local-Bus) (Local-Bus) (Local-Bus)
Fig4.2.3 Fig4.2.3 EPI PCB Block Diagram Fig4.2.3 Fig4.2.3
FPGA FPGA FPGA FPGA
24 24 24
Digital
WPI
-TGC
US-Scan
Controller
TCI header TCI header
TCI header TCI header
sPCI-Bridge PCI-Bridge
EPI PCB Block Diagram EPI PCB Block Diagram EPI PCB Block Diagram
4 - 10
to MAP
8
TCI I/F
8
from MAP
Sound Data (I S)
2
Audio
DAC
Sig Sel
& AMP
33 33 33 33MHz 32bit PCI-Bus MHz 32bit PCI-Bus MHz 32bit PCI-Bus MHz 32bit PCI-Bus
TCIA
TCIB
to SP
L
R
L1E-EA0229