Pulse Modulation Assembly - HP 8340B Manual

PULSE MODULATION ASSEMBLY
A21
Pulse Modulator Driver
Pulse modulation
is
produced by the
A21 pulse
modulator driver assembly driving one of the
two
pulse modulators.
The
front panel pulse modulation input
Is
a
TTL
compatible
Input.
A
low
signal
on this input turns the
RF
off,
and
a
high turns the RF on. With no connection, the pulse
modulation input
Is internally pulled to
a
TTL high level.
When
a
low signal Is present
on
the pulse modulation input, the
A21
pulse
modulator driver
delivers
20
mA to one of the two pulse modulators. An output multiplexer on the
A21
assembly
directs the
20
mA modulator current to the A9 low band pulse modulator when the Instrument
is in
low band, or to
the pulse modulator
in
the
A16
mod/splitter when the synthesizer Is
In
high
band.
The
leveled instrument
pulse modulation capability
requires
timing signals be sent to the
ALC
assemblies. The
timing signals
coordinate
the
leveling operation with the pulse operation.
When
a
pulse
Is
Initiated,
three timing signals are generated on the
A21
pulse modulator driver assembly:
Sample/Hold Timing
This signal controls the sample/hold gate on
the
A25 detector assembly. It Is
adjusted to close the
gate (sample) when the
RF
pulse
is on and
open the gate (hold)
when the
RF
Is off.
The sample/
hold
output voltage represents the peak RF amplitude.
Bias Sample/Hold Timing
This signal controls the sample/hold gate on the
A22 assembly (applicable on HP 8341
B
Option
003
only).
It
Is
adjusted to close the gate (sample) when
the
RF pulse
is
on and
open the gate
(hold) when the RF
is
off.
The
signal keeps the
3RD
bias
constant when the RF output
Is
off.
Analog to Digital Converter (ADC) Timing
This signal
enables
the analog to digital
converter
on the
A27
level control assembly to monitor the
output of the sample/hold. The ADC
is
enabled when the
RF
is on, and for
1
ms after the RF
is
turned
off.
After
1
ms,
voltage droop renders the sample/hold value inaccurate.
Integrator Timing
This signal controls the integrate and hold
gate
on the
A26 linear modulator assembly
This gate
is
closed when the RF
is
on and stable
To speed response
time for narrow pulses, the gate is
held
closed for
a minimum
of 10
^s. The sample/hold maintains
a
valid
integrator Input after the pulse
is
turned
off
HP8340B/41B
Change
5 RF
Section Theory
of Operation
H'll/H-12