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Pin name Pin No.
Type
#DET
21
Output
#IRQ
22
Open-drain
output
#SCLK
23
Input
SDI
24
Input
SDO
25
Output
CDIN
26
Input
Analog
BPOUT
27
Output
Analog
V
28
Power
DD
supply (+)
S1C05251 TECHNICAL MANUAL
Power-down
status
Active
Detection Output: When the device is in the power down mode and
the MODE1 pin is set to low level, low level at this pin indicates the
presence of ring signal or phone line reversal. If the MODE1 pin is set
to high level, low level at this pin indicates the presence of ring signal
or FSK inbound signal. When in the power up mode and FSK mode is
selected, low level at this pin indicates the presence of FSK inbound
signal. If CPM mode is selected, pulses from this pin indicate the
presence of CPM tone signal. If CAS mode is selected, low level at
this pin indicates the presence of CAS tone signal. Refer to Table
3.2.1 for more details.
Active
Interrupt Request Output: When the device is in the power down
mode, low level at this pin indicates the presence of ring signal or
phone line reversal. When in the power up mode and FSK mode is
selected, low level at this pin indicates that the received data is ready
in the internal register for the host device to read. In this mode, this pin
is set to high level after the first bit of the received data is read. If CPM
mode is selected, low level at this pin indicates the presence of CPM.
If CAS mode is selected, low level at this pin indicates that the CAS
tone is detected. In this mode, this pin remains low level while CAS
tones exist. Refer to Table 3.2.1 for more details.
Active
Serial Clock Input: The host device supplies a clock to this pin to
write internal registers or to read received data. The received data
changes its state at falling edge of the clock supplied by the host
device.
Active
Serial Data Input: The host device writes control bits through this pin.
High level Serial Data Output: The host device reads the serial receive data
from this pin. If asynchronous mode is selected, the asynchronous
format serial data appears at this pin. If synchronous mode is
selected, the received serial data is read from this pin by the host
device with the serial clock supplied to the #SCLK pin. During the
power down, CPM or CAS mode, this output pin is set to high level.
Capacitor Input: A 0.1 µF capacitor is connected between this pin
V
REF
and the BPOUT pin. The FSK signal can be applied from the FB pin
to this pin through this 0.1 µF capacitor to bypass the band pass filter
for internal testing purpose. Do not connect any external components
except this capacitor to this pin. Excess load may cause improper
operation of the circuit.
Capacitor Output: A 0.1 µF capacitor is connected between this pin
High-Z
and the CDIN pin. The band pass filter output is monitored at this pin
for internal testing purpose. Do not connect any external components
except this capacitor to this pin. Excess load may cause improper
operation of the circuit.
Device Power Supply: Positive power supply pin.
EPSON
1 OVERVIEW
Description
5
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