Fsk Demodulated Data Read Mode; Cas Detection Circuit Control-Register Write Mode - Epson S1C05251 Technical Manual

5.9.2 FSK Demodulated Data Read Mode

The FSK signal fed to the INP and INN pins is demodulated into 8-bit asynchronous (start-stop) data. The
demodulated data is then sampled by the internal 8-bit shift register. When the data has been stored in the shift
register, the #IRQ pin changes to Low level, indicating that the data can be read by the host CPU.
If the MODE pin is set to Low level and synchronoµs mode has been selected (MDR[0] = 1), the host CPU reads
out the 8-bit data synchronously with the clock signal fed from the host CPU to the #SCLK pin. Figure 5.9.3 shows
the timing at which this data is read. Each bit of the 8-bit data is output from the SDO pin synchronously with
falling edges of the #SCLK clock signal, beginning with bit 0. The host CPU latches each bit into the internal logic
at rising edges of the #SCLK clock signal.
If the MODE pin is set to Low level and asynchronous mode has been set (MDR[0] = 0), the data is output from the
SDO pin at a transfer rate of 1,200 baud. The clock signal from the host CPU is unnecessary. The host CPU latches
the data synchronously with the start bit.
Receive data
SDO
#SCLK
#IRQ
MODE0
SDO
#SCLK
#IRQ
MODE0

5.9.3 CAS Detection Circuit Control-Register Write Mode

The host CPU can write 4-bit data to the internal registers through the SDI pin in order to set each control bit. The
host CPU must temporarily pull the MODE pin to Low level to initialize the write control circuit before it can write
data. Then, after releasing the MODE pin back to High level, the host CPU must be held at High level while writing
data to the internal register. The data input to the SDI pin is sampled at rising edges of the clock signal fed from the
host CPU to the #SCLK pin. The first four bits of data sent from the host CPU are the address A[3:0] of the internal
register to be accessed. The subsequent four bits are the data bits D[3:0] to be written to the specified register. The
data is input beginning with the LSB.
SDI
#SCLK
Low level
MODE0
S1C05251 TECHNICAL MANUAL
417 µsec
High on rising edge of stop bit
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
#IRQ changes to High level on the first rise of #SCLK.
#IRQ→Low
Figure 5.9.3 Data read timing in synchronous mode
start BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 stop
Figure 5.9.4 Data read timing in asynchronous mode
First data
A0 A1 A2 A3 D0
Figure 5.9.5 Data write timing
5 ELECTRICAL CHARACTERISTICS
Stop bit
FSK/read mode
FSK/read mode
Second data
D1 D2 D3 A0 A1
CAS/write mode
EPSON
CAS/write mode
CAS/write mode
n'th data
A2 D3
FSK/read mode
25