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3 FUNCTIONAL DESCRIPTION
TLR, THR: Detection Threshold Setting Registers (Address = 3h, 4h)
Bit
Bit name
D0
TL0
D1
TL1
D2
TL2
D3
TL3
D0
TH0
D1
X
D2
X
D3
X
AVR: Average Divide-Ratio Select Register (Address = 5h)
Bit
Bit name
D0
AV0
D1
AV1
D2
AV2
D3
X
10
Table 3.1.5 TLR and THR registers
Initial
value
0110
CAS detection threshold selection
These bits control the minimum duration of tone with which the CAS tone is
identified. TH0 (THR register bit 0) is the MSB of the threshold set.
TH0
TL3
TL2
XXX1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
The bit setting 10110 corresponds to Bellcore and British Telecom Loop State
service; the bit setting 11001 corresponds to British Telecom Idle State service.
Table 3.1.6 AVR register
Initial
value
X011 Average counter divide-ratio selection
These bits control the frequency divide ratio of the internal average counter.
Setting to 011 is recommended.
AV2 AV1
AV0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Description
TL1
TL0
Threshold value (msec)
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Invalid (Cannot be set)
Description
Divide ratio
1/1
1/2
1/4
1/8
1/16
1/32
1/64
EPSON
5
9
12
16
19
21
23
26
29
32
34
36
39
43
46
48
50
53
56
59
61
64
67
70
73
76
78
81
84
87
90
S1C05251 TECHNICAL MANUAL
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