Ring/Line Reversal Signal Detection; Fsk Demodulation - Epson S1C05251 Technical Manual

3.4 Ring/Line Reversal Signal Detection

Figure 3.4.1 shows a typical circuit used to detect the Bellcore ring signal and British Telecom Line Reversal signal.
When the S1C05251 is in power-down mode, this circuit detects the ring signal or Line Reversal signal. The Line
Reversal or ring signal causes the voltage on the RDIN pin to rise, which drives the Schmitt rigger output high. This
causes the Nch transistor to turn on and the #RDRC pin to change to Low level. Since the RDIN pin is normally at
the V level, the #RDRC pin is at the High level. When the ring signal is input or the Line Reversal signal is
SS
generated, the capacitor of the #RDRC pin discharges, causing the #RDRC pin to change state from High to Low.
The #RDET pin operates in the same way, except that in any mode other than power-down mode, the #RDET pin
always responds to input on the RDIN pin.
TIP
RING

3.5 FSK Demodulation

The received FSK-modulated signal, after being processed by the band-pass filter, is demodulated by the FSK
demodulation circuit. If the FSK signal is input when the PDWN pin is set to Low level and FSK mode has been
selected by the host CPU, the #DET pin changes to Low level. The received data is read out from the SDO pin by
the host CPU. Also, the #IRQ pin is driven Low each time one byte is received. This demodulation circuit supports a
FSK-modulated signal that conforms to ITU-T V.23 or Bell202.
Parameter
Mark frequency
Space frequency
Receive signal level
Signal distortion
Transfer rate
S1C05251 TECHNICAL MANUAL
0.2 µF
470 kΩ
V
33 kΩ
0.2 µF
Figure 3.4.1 Ring/line reversal signal detection circuit
Table 3.5.1 FSK data characteristics
Bellcore
1200 Hz ±1%
2200 Hz ±1%
Mark: -32 dBm to -12 dBm
Space: -36 dBm to -12 dBm
≥ 25 dB
1200 baud ±1%
RDIN
DD
270 kΩ
V
DD
#RDRC
0.2 µF
1300 Hz ±1.5%
2100 Hz ±1.5%
Mark:
Space: -36 dBV to -8 dBV
≥ 20 dB
1200 baud ±1%
EPSON
3 FUNCTIONAL DESCRIPTION
#RDET
V
DD
#IRQ
#DET
BT
-40 dBV to -14 dBV
15