Functional Description; Register Description - Epson S1C05251 Technical Manual

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Functional Description

3.1 Register Description

The S1C05251 contains eight 4-bit registers that can be accessed by the CPU.
The CPU can access these CPU interface registers through the serial interface pins (SDI, #SCLK, and MODE0) and
control the mode of the S1C05251. The CPU uses the first four bits of transmit data to specify the address A[3:0] of
the internal register to be accessed. The data is transmitted beginning with the LSB (A0). The four bits that follow
the LSB are data bits D[3:0] which are the data to be written to the specified register. This data is also transmitted
beginning with the LSB (D0).
Table 3.1.1 shows registers and control bit assignments.
Register Address
name A[3:0]
MDR
GLR
GHR
TLR
THR
AVR
WLR
WHR
S1C05251 TECHNICAL MANUAL
Table 3.1.1 Register structure
Initial value
0000 0000
0001 0100
0010 0100
0011 0110
0100 XXX1
0101 X011
0110 0001
0111 0001
Data bit
D3 D2
TEST SEL
GL3 GL2
GH3 GH2
TL3 TL2
X X
X AV2
WL3 WL2
WH3 WH2
EPSON
3 FUNCTIONAL DESCRIPTION
D1 D0
BT SYNC
GL1 GL0
GH1 GH0
TL1 TL0
X TH0
AV1 AV0
WL1 WL0
WH1 WH0
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