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Philips Semiconductors
9397 750 09238
Product data
Table 5:
Set mode command, Configuration byte: bit allocation
Bit
Symbol
7 to 6
ENDPOINT
CONFIGURAT
ION
4
SoftConnect
3
INTERRUPT
MODE
2
CLOCK
RUNNING
1
NO
LAZYCLOCK
7 6
0 0
See
Table 6
for bit allocation.
Fig 7. Set mode command, Clock division factor byte.
Rev. 08 — 20 December 2001
USB interface device with parallel bus
Description
These two bits set the endpoint configurations as follows:
mode 0 (Non-ISO mode)
mode 1 (ISO-OUT mode)
mode 2 (ISO-IN mode)
mode 3 (ISO-I/O mode)
See
Section 8 "Endpoint description"
A '1' indicates that the upstream pull-up resistor will be connected
if V
is available. A '0' means that the upstream resistor will not
BUS
be connected. The programmed value will not be changed by a
bus reset.
A '1' indicates that all errors and "NAKing" are reported and will
generate an interrupt. A '0' indicates that only OK is reported. The
programmed value will not be changed by a bus reset.
A '1' indicates that the internal clocks and PLL are always running
even during Suspend state. A '0' indicates that the internal clock,
crystal oscillator and PLL are stopped whenever not needed. To
meet the strict Suspend current requirement, this bit needs to be
set to '0'. The programmed value will not be changed by a bus
reset.
A '1' indicates that CLKOUT will not switch to LazyClock. A '0'
indicates that the CLKOUT switches to LazyClock 1ms after the
Suspend pin goes HIGH. LazyClock frequency is 30 kHz ± 40%.
The programmed value will not be changed by a bus reset.
5
4
3
2
1
0
X X
1
0
1
1
POWER ON VALUE
CLOCK DIVISION FACTOR
RESERVED
SET_TO_ONE
SOF-ONLY INTERRUPT MODE
PDIUSBD12
for more details.
SV00862
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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