Toshiba TXZ+ TMPM4MNFYAFG Reference Manual page 5

TXZ+ Family
TMPM4M Group(1)
Clock Control and Operation Mode
List of Figures
Figure 1.1 Clock system diagram............................................................................................................. 12
Figure 1.2 Mode state transition............................................................................................................... 25
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation mode transition ......................................... 29
Figure 2.1 TMPM4MxFYA ........................................................................................................................ 44
Figure 2.2 TMPM4MxFWA ....................................................................................................................... 45
Figure 2.3 Single chip mode .................................................................................................................... 47
Figure 2.4 Single boot mode .................................................................................................................... 48
Figure 3.1 The reset operation by a Power On Reset Circuit .................................................................. 53
Figure 3.2 Reset operation by a RESET_N pin (1) .................................................................................. 54
Figure 3.3 Reset operation by a RESET_N pin (2) .................................................................................. 55
Figure 3.4 Reset operation by LVD reset ................................................................................................. 56
Figure 3.5 Warm reset operation ............................................................................................................. 57
Figure 3.6 When the power supply is on, starting in single boot mode by the RESET_N pin ................ 58
Figure 3.7 Starting in the single boot mode when power supply is stable............................................... 59
Figure 3.8 Power On Reset Circuit .......................................................................................................... 60
List of Tables
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> setup .................................................................... 15
Table 1.2 PLL correction (example) ......................................................................................................... 15
Table 1.3 PLL0SET setting value (example) ........................................................................................... 16
Table 1.4 Clock domains of CPU and peripherals ................................................................................... 18
Table 1.5 Time interval for changing System clock ................................................................................. 18
Table 1.6 Example of operation frequency .............................................................................................. 18
Table 1.7 Operating frequency examples of High speed and Middle speed system clocks ................... 19
Table 1.8 Time interval for changing prescaler clocks ............................................................................ 21
Table 1.9 Low Power Consumption mode selection................................................................................ 23
Table 1.10 Block operation status in each Low Power Consumption mode ........................................... 24
Table 1.11 Release source list ................................................................................................................. 27
Table 1.12 Warming-up ............................................................................................................................ 28
Table 1.13 [CGFSYSMENA] register corresponding to each product ..................................................... 40
Table 1.14 [CGFSYSMENB] register corresponding to each product ..................................................... 41
Table 1.15 [CGFSYSENA] register corresponding to each product ........................................................ 42
Table 1.16 [CGFCEN] register corresponding to each product ............................................................... 42
Table 2.1 Single chip mode ...................................................................................................................... 49
Table 2.2 Single boot mode ..................................................................................................................... 49
Table 2.3 Single chip mode ...................................................................................................................... 50
Table 2.4 Single boot mode ..................................................................................................................... 50
Table 2.5 Connection of peripheral function ............................................................................................ 51
Table 3.1 The reset factor and the range initialized................................................................................. 62
Table 4.1 Revision History ....................................................................................................................... 63
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