1.5.3. [CGFSYSENA]
Table 1.15 [CGFSYSENA] register corresponding to each product
Bit
Bit Symbol
1
IPENA01
0
IPENA00
Note: : Available, -: N/A
1.5.4. [CGFCEN]
Bit
Bit Symbol
28
FCIPEN28
27
FCIPEN27
26
FCIPEN26
23
FCIPEN23
Note: : Available, -: N/A
Internal connection
peripheral circuit
RAMP
CRC
Table 1.16 [CGFCEN] register corresponding to each product
Internal connection
peripheral circuit
DNF
OFD
Clock Control and Operation Mode
Channel No./
Unit name/
M4MN
Port name
0
-
Channel No./
Unit name/
M4MN
Port name
C
B
A
-
42 / 64
TXZ+ Family
TMPM4M Group(1)
M4MM
M4ML
M4MM
M4ML
2022-06-24
Rev. 1.1