Cgfsysena] (Clock Supply And Stop Register A For Fsys) - Toshiba TXZ+ Series Reference Manual

1.4.2.10. [CGFSYSENA] (Clock supply and stop register A for fsys)

Bit Bit Symbol
31 IPENA31
30 IPENA30
29 IPENA29
28 IPENA28
27 IPENA27
26 IPENA26
25 IPENA25
24 IPENA24
23 IPENA23
22 IPENA22
21 IPENA21
20 IPENA20
19 IPENA19
18 IPENA18
17 IPENA17
16 IPENA16
15 IPENA15
14 IPENA14
13 IPENA13
12 IPENA12
After
Type
reset
Enable the Clock of T32A channel7
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel6
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel5
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel4
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel3
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel2
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel1
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of T32A channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of RTC
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of RMC channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of A-ENC channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of A-PMD channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of DMAC Unit B
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of DMAC Unit A
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of PORT V
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of PORT U
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of PORT T
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of PORT R
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of PORT P
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of PORT N
0 R/W 0: Clock stop
1: Clock supply
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TMPM3H Group(1)
Clock Control and Operation Mode
Function
TXZ+ Family
2022-05-10
Rev. 1.3