The product will be cut off the power except for the following circuit in STOP2 mode.
●
External low speed oscillator (ELOSC)
●
RTC
●
Backup RAM
●
Port pin status
●
LVD
●
RLM
●
IA
●
I2C Wake up
●
LCD
Regarding a power supply cutoff in the Low power Consumption mode, for details, refer to "1.3.1.4. The
peripheral function state in a Low power consumption mode".
1.3.1.2. Low Power Consumption mode
In order to shift to each Low Power Consumption mode, the IDLE/STOP1/STOP2 mode is chosen by standby
control register [CGSTBYCR]<STBY[1:0] >, and a WFI command is executed. When it shifts to a Low Power
Consumption mode by WFI command, the restart operation from a Low Power Consumption mode is performed
by reset or interrupt generating. To return by an interrupt, it is necessary to set up. Please refer to "Interrupt"
chapter of the reference manual "Exception" for details.
Note1: This product does not support a return by events; therefore, do not make a transition to low-power
consumption mode triggered by WFE (Wait For Event).
Note2: This product does not support low-power consumption mode by SLEEPDEEP of the Cortex-M3 core.
Do not use the <SLEEPDEEP> bit of the system control register.
1.3.1.3. Selection of a Low Power Consumption mode
Low Power Consumption mode selection is chosen by the setup of [CGSTBYCR]<STBY [1:0]>.
Following table shows the mode chosen from a setup of <STBY [1:0]>.
Note: Do not use the settings other than the above.
1.3.1.4. The peripheral function state in a Low power consumption mode
The following Table 1.7 shows the Operation State of the peripheral function (block) in each mode.
In addition, after reset release it will be in the state where a clock is not supplied except for a part of blocks.
If needed, set up [CGFSYSENA], [CGFSYSENB], [CGFSYSMENB], [CGFCEN] and [CGSPCLKEN] and
enable clock supply.
Table 1.6 Low Power Consumption mode selection
Mode
IDLE
STOP1
STOP2
23 / 72
Clock Control and Operation Mode
[CGSTBYCR]<STBY[1:0]>
00
01
10
TXZ+ Family
TMPM3H Group(1)
2022-05-10
Rev. 1.3