2.2.1.2. Single boot mode
Code Flash
Data Flash
RAM0
RAM1
RAM2
Backup RAM
BOOT ROM
TSPI (ch0/1)
I2C, EI2C (ch0)
UART (ch0/1/2/3)
T32A (ch0/1/2/3)
TSPI (ch2/3/4)
I2C, EI2C (ch1/2/3)
UART (ch4/5/6/7)
T32A (ch4/5/6/7)
CRC
DMAC (SFR)
SIWDT
TRGSEL
DNF
RAMP (SFR)
DMAC
(unitB)
DMAC
(unitA)
S0
S1
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
APB
M12
APB
M13
APB
M14
S0
S1
Figure 2.5 Single boot mode
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Clock Control and Operation Mode
Cortex-M3
System
Data
Instruction
S2
S3
S4
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
S2
S3
S4
TXZ+ Family
TMPM3H Group(1)
GPREG
LCD
IA (INTIF)
I2CS
RLM
LVD
AO
APB
ADC
DAC
COMP
IO
CG
IB (INTIF)
IMN
PORT
A-PMD
A-ENC
RMC
RTC
OFD
Flash (SFR)
TRM
2022-05-10
Rev. 1.3